ST7FLITE39M6TR STMicroelectronics, ST7FLITE39M6TR Datasheet - Page 45
![IC MCU 8BIT 8K FLASH 20SOIC](/photos/6/56/65691/497-20-soic__7_5mm_width__series_sml.jpg)
ST7FLITE39M6TR
Manufacturer Part Number
ST7FLITE39M6TR
Description
IC MCU 8BIT 8K FLASH 20SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Specifications of ST7FLITE39M6TR
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST7FLITE3x
Core
ST7
Data Bus Width
8 bit
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
For Use With
497-8403 - BOARD DEMO STCC08 AC SW DETECTOR497-6398 - BOARD EVAL ST7FLITE39/STM1403497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FLITE39M6TR
Manufacturer:
IDT
Quantity:
2 799
Part Number:
ST7FLITE39M6TR
Manufacturer:
ST
Quantity:
20 000
POWER SAVING MODES (Cont’d)
Figure 30. AWUFH Mode Flow-chart
(AWUCSR.AWUEN=1)
HALT INSTRUCTION
(Active-Halt disabled)
N
WATCHDOG
WDGHALT
RESET
1
INTERRUPT
Y
1)
ENABLE
3)
OR SERVICE INTERRUPT
0
FETCH RESET VECTOR
AWU RC OSC
MAIN OSC
PERIPHERALS
AWU RC OSC
MAIN OSC
PERIPHERALS
MAIN OSC
PERIPHERALS
CPU
I[1:0] BITS
CPU
I[1:0] BITS
AWU RC OSC
CPU
I[1:0] BITS
N
256 CPU CLOCK
CYCLE
RESET
Y
WATCHDOG
DELAY
DISABLE
2)
XX
XX
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
10
4)
4)
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only an AWUFH interrupt and some specific in-
terrupts can exit the MCU from HALT mode (such
as external interrupt). Refer to Table 6, “Interrupt
Mapping,” on page 36 for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
ST7LITE3xF2
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