ST7FLITE09Y0M6 STMicroelectronics, ST7FLITE09Y0M6 Datasheet - Page 64
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ST7FLITE09Y0M6
Manufacturer Part Number
ST7FLITE09Y0M6
Description
MCU 8BIT 1.5KB FLSH 128KB 16SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLITES2Y0B6.pdf
(124 pages)
Specifications of ST7FLITE09Y0M6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (3.9mm Width)
Processor Series
ST7FLITE0x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Operating Supply Voltage
2.4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLIT0-IND/USB, ST7FLIT2-COS/COM, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
For Use With
497-6250 - BOARD RGB COLOR CTRL STP04CM596497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-5633-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FLITE09Y0M6
Manufacturer:
DIODES
Quantity:
43 000
Part Number:
ST7FLITE09Y0M6
Manufacturer:
ST
Quantity:
20 000
ST7LITE0xY0, ST7LITESxY0
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.5 Error Flags
11.3.5.1 Master Mode Fault (MODF)
Master mode fault occurs when the master device
has its SS pin pulled low.
When a Master mode fault occurs:
Clearing the MODF bit is done through a software
sequence:
1. A read access to the SPICSR register while the
2. A write to the SPICR register.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their orig-
inal state during or after this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
11.3.5.2 Overrun Condition (OVR)
An overrun condition occurs, when the master de-
vice has sent a data byte and the slave device has
Figure 42. Clearing the WCOL bit (Write Collision Flag) Software Sequence
64/124
1
1st Step
2nd Step
– The MODF bit is set and an SPI interrupt re-
– The SPE bit is reset. This blocks all output
– The MSTR bit is reset, thus forcing the device
quest is generated if the SPIE bit is set.
from the device and disables the SPI periph-
eral.
into slave mode.
MODF bit is set.
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
2nd Step
Read SPICSR
Read SPIDR
RESULT
SPIF =0
WCOL=0
Read SPIDR
Read SPICSR
RESULT
WCOL=0
not cleared the SPIF bit issued from the previously
transmitted byte.
When an Overrun occurs:
– The OVR bit is set and an interrupt request is
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
The OVR bit is cleared by reading the SPICSR
register.
11.3.5.3 Write Collision Error (WCOL)
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.
Write collisions can occur both in master and slave
mode. See also
Management.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see
generated if the SPIE bit is set.
Note: Writing to the SPIDR regis-
ter instead of reading it does not
reset the WCOL bit
Figure
Section 11.3.3.2 Slave Select
42).