EZ80F93AZ020SC00TR Zilog, EZ80F93AZ020SC00TR Datasheet - Page 143
EZ80F93AZ020SC00TR
Manufacturer Part Number
EZ80F93AZ020SC00TR
Description
IC ACCLAIM MCU 64KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F93AZ020SC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
EZ80F93AZ020SC00T
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PS015313-0508
A Write to either the Low or High byte registers for the BRG Divisor Latch causes both
bytes to be loaded into the BRG counter and the count restarted. See
73.
Table 72. SPI Baud Rate Generator Register—Low Byte(SPI_BRG_L = 00B8h)
sterister is used to control and setup the serial peripheral interface. The SPI should be dis-
Table 73. SPI Baud Rate Generator Register—High Byte (SPI_BRG_H = 00B9h)
This register is used to control and setup the serial peripheral interface. The SPI should be
disabled prior to making any changes to CPHA or CPOL. See disabled prior to making
any changes to CPHA or CPOL. See
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
SPI_BRG_L
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
SPI_BRG_H
Value
00h–
FFh
Value
00h–
FFh
R/W
Description
These bits represent the Low byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {SPI_BRG_H, SPI_BRG_L}.
R/W
Description
These bits represent the High byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {SPI_BRG_H, SPI_BRG_L}.
7
0
7
0
R/W
R/W
6
0
6
0
Table 74
R/W
R/W
5
0
5
0
on page 137.
R/W
R/W
4
0
4
0
R/W
R/W
3
0
3
0
Product Specification
Serial Peripheral Interface
R/W
R/W
Table 72
2
0
2
0
eZ80F92/eZ80F93
R/W
R/W
1
1
1
0
and
Table
R/W
R/W
0
0
0
0
136
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