ST72F63BE6M1 STMicroelectronics, ST72F63BE6M1 Datasheet - Page 135

• Manufacturer Part Number: ST72F63BE6M1
• Description: IC MCU 8BIT 32K FLASH 24-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F63BE6M1

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-SOIC (7.5mm Width)
• Data Converters: A/D 12x8b
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
• Minimum Operating Temperature: 0 C
• For Use With: 497-5521 - EVAL BOARD LOW SPEED USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST7263Bxx
12.2
Instruction groups
The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions
may be subdivided into 13 main groups as illustrated in the following table:
Table 53.
Using a pre-byte
The instructions are described with one to four bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
The whole instruction becomes:
These prebytes enable instruction in Y as well as indirect addressing modes to be
implemented. They precede the opcode of the instruction in X or the instruction using direct
addressing mode. The prebytes are:
Condition Code Flag modification
Conditional Bit Test and Branch
Unconditional Jump or Call
Interruption management
PC-2End of previous instruction
PC-1Prebyte
PCOpcode
PC+1Additional word (0 to 2) according to the number of bytes required to compute the
effective address
PDY 90Replace an X based instruction using immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92Replace an instruction using direct, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using
indirect X indexed addressing mode.
PIY 91Replace an instruction using X indirect indexed addressing mode by a Y one.
Increment/Decrement
Arithmetic operations
Compare and Tests
Conditional Branch
Load and Transfer
Logical operations
Shift and Rotates
Stack operation
Bit Operation
Instruction groups
Doc ID 7516 Rev 8
PUSH
TRAP
BSET
BTJT
JRxx
AND
ADC
JRA
SLL
SIM
INC
CP
LD
BRES
BTJF
DEC
ADD
CLR
POP
TNZ
SRL
JRT
WFI
RIM
OR
HALT
XOR
RSP
BCP
SUB
SRA
SCF
JRF
IRET
SBC
RLC
RCF
CPL
JP
CALL
NEG
MUL
RRC
CALLR
SWAP
Instruction set
NOP RET
SLA
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