ST72F561K9T3 STMicroelectronics, ST72F561K9T3 Datasheet - Page 48
ST72F561K9T3
Manufacturer Part Number
ST72F561K9T3
Description
IC MCU 8BIT 60K FLASH 32-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F561K6T6.pdf
(265 pages)
Specifications of ST72F561K9T3
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
32-LQFP
Processor Series
ST72F5x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
497-8374 - BOARD DEVELOPMENT FOR ST72F561
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F561K9T3
Manufacturer:
STMicroelectronics
Quantity:
10 000
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ST72561
I/O PORTS (Cont’d)
Table 13. I/O Port Configurations
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
48/265
reading the DR register will read the alternate function output status.
the alternate function reads the pin status given by the DR register content.
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
PAD
PAD
PAD
V
V
V
DD
R
DD
DD
R
R
PU
PU
PU
PULL-UP
CONDITION
Hardware Configuration
INTERRUPT
CONDITION
ALTERNATE
ALTERNATE
REGISTER
ENABLE
ENABLE
DR
DR REGISTER ACCESS
EXTERNAL INTERRUPT
SOURCE (ei
REGISTER
REGISTER
DR
DR
DR REGISTER ACCESS
DR REGISTER ACCESS
W
R
x
ALTERNATE
ALTERNATE
)
OUTPUT
OUTPUT
ALTERNATE INPUT
ANALOG INPUT
R/W
R/W
DATA BUS
DATA BUS
DATA BUS
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