ST10R272LT1 STMicroelectronics, ST10R272LT1 Datasheet - Page 14

• Manufacturer Part Number: ST10R272LT1
• Description: MCU 16BIT ROMLESS LV 100-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R272LT1

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: ST10
• No. Of I/o's: 77
• Ram Memory Size: 1KB
• Cpu Speed: 50MHz
• No. Of Timers: 5
• Embedded Interface Type: SPI, USART
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST10R2x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SSP, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 16 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)
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The MAC is a specialized co-processor added to the ST10R272L CPU core to improve the
performance of signal processing algorithms. It includes:
•
•
•
New addressing capabilities enable the CPU to supply the MAC with up to 2 operands per
instruction cycle. MAC instructions: multiply, multiply-accumulate, 32-bit signed arithmetic
operations and the CoMOV transfer instruction have been added to the standard instruction
set. Full details are provided in the ‘ST10 Family Programming Manual’.
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a multiply-accumulate unit
an address generation unit, able to feed the mac unit with 2 operands per cycle
a repeat unit, to execute a series of multiply-accumulate instructions
MULTIPLY-ACCUMULATE UNIT (MAC)
internal RAM
dual-port
Peripheral
interface
data buses
40-bit ALU
multiplier
16 x16
shifter
operands
Figure 5 MAC architecture
new addressing features
ST10R272L CPU
IDX0
IDX1
MAC CoProcessor
MCW MAL
MRW MAH
QX0
QX1
MSW
control
QR0
QR1
40-bit accumulator
repeat unit
program code
external
memory
program
memory