ST10R272LT1 STMicroelectronics, ST10R272LT1 Datasheet - Page 9

• Manufacturer Part Number: ST10R272LT1
• Description: MCU 16BIT ROMLESS LV 100-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R272LT1

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: ST10
• No. Of I/o's: 77
• Ram Memory Size: 1KB
• Cpu Speed: 50MHz
• No. Of Timers: 5
• Embedded Interface Type: SPI, USART
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST10R2x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SSP, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 16 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

RSTIN
RSTOUT
NMI
P6.0-
P6.7
79
80
81
82-89
82
...
86
87
88
89
I
O
I
I/O
O
...
O
I
I/O
O
5T
5T
5S
5T
5T
...
5T
5T
5T
5T
Table 1 Pin definitions
Reset Input with Schmitt-Trigger characteristics. Resets the
device when a low level is applied for a specified duration while
the oscillator is running. An internal pullup resistor enables
power-on reset using only a capacitor connected to
a bonding option, the RSTIN pin can also be pulled-down for
512 internal clock cycles for hardware, software or watchdog
timer triggered resets
Internal Reset Indication Output. This pin is set to a low level
when the part is executes hardware-, software- or watchdog
timer reset. RSTOUT remains low until the EINIT (end of ini-
tialization) instruction is executed.
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine.
If it is not used, NMI should be pulled high externally.
An 8-bit bidirectional I/O port. Port 6 is bit-wise programmable
for input or output via direction bits. For a pin configured as
input, the output driver is put into high-impedance state. Port 6
outputs can be configured as push/pull or open drain drivers.
The following Port 6 pins have alternate functions:
P6.0
...
P6.4
P6.5
P6.6
P6.7
CS0
...
CS4
HOLD
HLDA
BREQ
Chip Select 0 Output
...
Chip Select 4 Output
External Master Hold Request Input
(Master mode: O, Slave mode: I)
Hold Acknowledge Output
Bus Request Output
ST10R272L - PIN DESCRIPTION
V
SS
.
With
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