STR912FAW44X6T STMicroelectronics, STR912FAW44X6T Datasheet - Page 2

• Manufacturer Part Number: STR912FAW44X6T
• Description: MCU ARM9 512KB FLASH 128LQFP
• Manufacturer: STMicroelectronics
• Series: STR9r

Specifications of STR912FAW44X6T

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Processor Series: STR912x
• Core: ARM966E-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 96 KB
• Interface Type: CAN, I2C, IrDA, SSP, UART, USB
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, KSDK-STR912-PLUS, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: STR9-COMSTICK, STR910-EVAL, STR91X-SK/HIT, STR91X-SK/IAR, STR91X-SK/KEI, STR91X-SK/RAI, STR9-DK/RAIS, STR91X-DK/IAR, STX-PRO/RAIS, STR912-D/RAIS, STR79-RVDK/CPP, STR79-RVDKCPP/9, STR79-RVDK, STR79-RVDK/9, STR9-RVDK/BAS, STR79-RVDK/UPG
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES497-5067 - BOARD EVAL FOR STR910 FAMILY497-5066 - KIT STARTER KEIL FOR STR910497-5065 - KIT STARTER IAR KICKSTART STR912497-5064 - KIT STARTER FOR STR910 FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Contents
Contents
1
2
3
2/102
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
System-in-a-package (SiP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ARM966E-S CPU core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Burst Flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4.1
3.4.2
3.4.3
SRAM (64 Kbytes or 96 Kbytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.1
3.5.2
DMA data movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Non-volatile memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7.1
3.7.2
One-time-programmable (OTP) memory . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8.1
Vectored interrupt controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9.1
3.9.2
3.9.3
Clock control unit (CCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10.1
3.10.2
3.10.3
3.10.4
3.10.5
3.10.6
3.10.7
Pre-fetch queue (PFQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Branch cache (BC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Management of literals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Primary Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Secondary Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Product ID and revision level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FIQ handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
IRQ handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Master clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reference clock (RCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AHB clock (HCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
APB clock (PCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Flash memory interface clock (FMICLK) . . . . . . . . . . . . . . . . . . . . . . . . 22
UART and SSP clock (BRCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
External memory interface bus clock (BCLK) . . . . . . . . . . . . . . . . . . . . 22
Doc ID 13495 Rev 6
STR91xFAxxx