str912fa STMicroelectronics, str912fa Datasheet
str912fa
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str912fa Summary of contents
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ARM966E-S™ 16/32-Bit Flash MCU with Ethernet, USB, CAN, Features ■ 16/32-bit 96 MHz ARM9E based MCU – ARM966E-S RISC core: Harvard archi- tecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash) – STR91xFA implementation of core adds high-speed burst Flash memory ...
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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STR91xFA 2.10.10 External RTC calibration clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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General purpose I ...
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STR91xFA 6.11 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... CAN, EMI, functions 40 I/Os 80 I/Os LQFP LQFP LFBGA Packages 80 128 6/78 STR911FA 256 512 256 +32 +32 +32 96 USB, CAN, USB, CAN, 40 I/Os EMI, 80 I/Os LQFP80 LQFP128 144 STR912FA 512 512 256 512 +32 +32 +32 + Ethernet, USB, CAN, EMI,80 I/Os LQFP128 STR91xFA 256 512 +32 +32 LFBGA144 ...
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STR91xFA 2 Functional overview 2.1 System-in-a-Package (SiP) The STR91xFA is a SiP device, comprised of two stacked die. One die is the ARM966E-S CPU with peripheral interfaces and analog functions, and the other die is the burst Flash. The two ...
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Functional overview 2.4.2 Branch Cache (BC) When instruction addresses are not sequential, such as a program branch situation, the PFQ would have to flush and reload which would cause the CPU to stall were present. Before reloading, ...
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STR91xFA Figure 1. STR91xFA block diagram 1.8V GND 3.0 or 3.3V GND VBATT 4 MHz to 25 MHz XTAL EMI Ctrl USB Bus To Ethernet PHY (MII USB not available on STR910 ** Ethernet MAC not available on ...
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Functional overview 2.5 SRAM (64K or 96K Bytes) A 32-bit wide SRAM resides on the CPU’s Data TCM (D-TCM) interface, providing single-cycle data accesses. As shown in High-performance Bus (AHB). Sharing is controlled by simple arbitration logic to allow the ...
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STR91xFA Flash memories are programmed half-word (16 bits time, but are erased by sector or by full array. 2.7.1 Primary Flash memory Using the STR91xFA device configuration software tool and 3rd party Integrated Developer Environments possible ...
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Functional overview values indicating memory size or other differentiating features. Byte 30 contains the silicon revision level indicator. See devices. See the Errata Sheet documents for STR91xF and STR91xFA for details of external identification of silicon revisions. Table 2. Product ...
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STR91xFA 2.9.3 Interrupt sources The 32 interrupt request signals coming into the VIC on 32 IRQ channels are from various sources; 5 from a wake-up unit and the remaining 27 come from internal sources on the STR91xFA such as on-chip ...
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Functional overview Table 3. VIC IRQ Channels IRQ Channel VIC input hardware channel priority 25 VIC1.9 26 VIC1.10 27 VIC1.11 28 VIC1.12 29 VIC1.13 30 VIC1.14 31 (low priority) VIC1.15 2.10 Clock control unit (CCU) The CCU generates a master ...
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STR91xFA As an option, there are a number of peripherals that do not have to receive a clock sourced from the CCU. The USB interface can receive an external clock on pin P2.7, TIM timers TIM0/ TIM1 can receive an ...
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Functional overview between the ARM core and the Flash memory. Typically, codes in the Flash memory can be fetched one word per FMICLK clock in burst mode. The maximum FMICLK frequency is 96MHz. 2.10.6 Baud rate clock (BRCLK) The baud ...
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STR91xFA at 48 MHz, and the Ethernet interface at 25 MHz. The RTC is always running in the background at 32.768 kHz, and the CPU can go to very low power mode dynamically by running from 32.768 kHz and shutting ...
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Functional overview 2.11.3 Sleep mode In this mode all clock circuits except the RTC are turned off and main oscillator input pins X1_CPU and X2_CPU are disabled. The RTC clock is required for the CPU to exit Sleep Mode. The ...
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... LVD threshold is 2.7V. The choice of trigger level is made DDQ by STR91xFA device configuration software from STMicroelectronics or IDE from 3rd parties, and is programmed into the STR91xFA device along with other configurable items through the JTAG interface when the Flash memory is programmed. ...
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Functional overview peripheral clock from the APB, and an 8-bit clock pre-scaler is available. When enabled by firmware as a watchdog, this timer will cause a system reset if firmware fails to periodically reload this timer before the terminal count ...
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STR91xFA an alternate power source, such as a battery, is connected to the VBATT input pin. The current drawn by the RTC unit on the VBATT pin is very low in this standby mode, I 2.15 JTAG interface An IEEE-1149.1 ...
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Functional overview Figure 3. JTAG chaining inside the STR91xFA JTDO JTRSTn JTCK JTMS JTDI JRTCK 2.15.1 In-system-programming The JTAG interface is used to program or erase all memory areas of the STR91xFA device. The pin RESET_INn must be asserted during ...
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STR91xFA itself. Debugging requires that an external host computer, running debug software, is connected to the STR91xFA target system via hardware which converts the stream of debug data and commands from the host system’s protocol (USB, Ethernet, etc.) to the ...
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Functional overview the host computer must have a static image of the code being executed for decompressing the ETM9 data. Because of this, self-modified code cannot be traced. 2.17 Ethernet MAC interface with DMA STR91xFA devices in 128-pin and 144-ball ...
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STR91xFA ● Supports USB low and full-speed transfers (12 Mbps), certified to comply with the USB 2.0 specification ● Supports isochronous, bulk, control, and interrupt endpoints ● Configurable number of endpoints allowing a mixture single-buffered monodirectional ...
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Functional overview SRAM, handling of transmission requests, and interrupt generation. The CPU has access to the Message SRAM via the Message Handler using a set of 38 control registers. The follow features are supported by the CAN interface: ● Bitrates ...
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STR91xFA 2 2. interfaces with DMA The STR91xFA supports two independent I2C serial interfaces, designated I2C0, and I2C1. Each interface allows direct connection to an I2C bus as either a bus master or bus slave device (firmware configurable). ...
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Functional overview high-impedance state when not selected. The STR91xFA supports SPI multi-Master operation because it provides collision detection. Each SSP interface on the STR91xFA has the following features: ● Full-duplex, three or four-wire synchronous transfers ● Master or Slave operation ...
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STR91xFA 2.24 A/D converter (ADC) with DMA The STR91xFA provides an eight-channel, 10-bit successive approximation analog-to-digital converter. The ADC input pins are multiplexed with other functions on Port 4 as shown in Table 5. Following are the major ADC features: ...
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Functional overview ● One pulse generation in response to an external event ● A dedicated interrupt to the CPU with five interrupt flags ● The OCF1 flag (Output Compare 1) from the timer can be configured to trigger an ADC ...
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STR91xFA The EMI has the following features: ● Supports static asynchronous memory access cycles, including page mode for non-mux operation. The bus control signals include: – EMI_RDn - read signal x16 mode – EMI_BWR_WRLn - write signal in ...
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Functional overview By defining the bus parameters such as burst length, burst type, read and write timings in the EMI control registers, the EMI bus is able to interface to standard burst memory devices. The burst timing specification and waveform ...
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STR91xFA Figure 6. EMI 8-bit non-multiplexed connection example STR91xx EMI_BWR_WRLn EMI_CS3n EMI_CS2n EMI_CS1n EMI_CS0n EMI_RDn P9.7 EMI_A15 P9.6 EMI_A14 P9.5 EMI_A13 P9.4 EMI_A12 P9.3 EMI_A11 P9.2 EMI_A10 P9.1 EMI_A9 P9.0 EMI_A8 P7.7 EMI_A7 P7.6 EMI_A6 P7.5 EMI_A5 P7.4 EMI_A4 P7.3 ...
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Related documentation 3 Related documentation Available from www.arm.com: ARM966E-S Rev 2 Technical Reference Manual Available from www.st.com: STR91xFA Reference Manual STR9 Flash Programming Manual (PM0020) The above is a selected list only, a full list STR91xFA application notes can be ...
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STR91xFA 4 Pin description Figure 7. STR91xFAM 80-pin package pinout P4.3 P4.2 P4.1 P4.0 VSS_VSSQ VDDQ P2.0 P2.1 P5.0 VSS VDD P5.1 P6.2 P6.3 VDDQ VSSQ P5.2 P5.3 P6.0 P6 (Not Used) on STR910FAM devices. Pin 59 is ...
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Pin description Figure 8. STR91xFAW 128-pin package pinout P4.2 P4.1 P4.0 AVSS P7.0 P7.1 P7.2 VSSQ VDDQ P2.0 P2.1 P5.0 P7.3 P7.4 P7.5 VSS VDD P5.1 P6.2 P6.3 EMI_BWR_WRLn EMI_WRHn VDDQ VSSQ (3) PHYCLK_P5.2 P8.0 P5.3 P8.1 P6.0 P8.2 P6.1 ...
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STR91xFA 4.1 LFBGA144 ball connections ● In Table 4. balls labelled NC are no connect balls. These NC balls are reserved for future devices and should NOT be connected to ground or any other signal. There are total of 9 ...
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... Output 1, 2, 3” of Notes for Table 5: Notes: 1 STMicroelectronics advises to ground, or pull pins on port reduce noise susceptibility, noise generation, and minimize power consumption. There are no internal or programmable pull-up resistors on ports 0-9. 2 All pins on ports are 5V tolerant 3 Pins on ports 0,1,2,4,5,7,8,9 have 4 mA drive and 4mA sink. Ports 3 and 6 have 8 mA drive and 8 mA sink ...
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STR91xFA Pkg Default Pin Pin Name Function GPIO_0. F11 P0.5 I/O GP Input, HiZ GPIO_0. E11 P0.6 I/O GP Input, HiZ GPIO_0. B12 P0.7 I/O GP Input, HiZ GPIO_1. B10 P1.0 I/O ...
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Pin description Pkg Default Pin Pin Name Function GPIO_3. M12 P3.6 I/O GP Input, HiZ GPIO_3. K11 P3.7 I/O GP Input, HiZ GPIO_4. P4.0 I/O GP Input, HiZ GPIO_4. P4.1 ...
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STR91xFA Pkg Default Pin Pin Name Function GPIO_6. P6.6 I/O GP Input, HiZ GPIO_6. D12 P6.7 I/O GP Input, HiZ GPIO_7. P7.0 I/O GP Input, HiZ GPIO_7. P7.1 I/O ...
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Pin description Pkg Default Pin Pin Name Function GPIO_9. P9.7 I/O GP Input, HiZ EMI byte write strobe (8 bit mode) or low EMI_BWR byte write strobe _WRLn (16 bit mode Can also ...
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STR91xFA Pkg Default Pin Pin Name Function JTAG mode 69 111 A6 JTMS I select 72 115 C6 JTDI I JTAG data in 73 117 B6 JTDO O JTAG data out ADC analog - 122 A3 AVDD V voltage source, ...
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Memory mapping 5 Memory mapping The ARM966E-S CPU addresses a single linear address space of 4 giga-bytes (2 address 0x0000.0000 to 0xFFFF.FFFF as shown in address 0x0000.0000, which is chip-select zero at address zero in the Flash Memory Interface (FMI). ...
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STR91xFA When other AHB bus masters (such as a DMA controller) write to SRAM, their access is never buffered. Only the CPU can make use of buffered AHB writes. 5.4 Two independent Flash memories The STR91xFA has two independent Flash ...
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Memory mapping Notes for Figure 9: STR91xFA memory map on page Notes: 1 Either of the two Flash memories may be placed at CPU boot address 0x0000.0000. By default, the primary Flash memory is in boot position starting at CPU ...
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STR91xFA Figure 9. STR91xFA memory map TOTAL 4 GB CPU MEMORY SPACE 0xFFFF.FFFF VIC0 0xFFFF.F000 RESERVED 0xFC01.0000 VIC1 0xFC00.0000 RESERVED 0x8000.0000 ENET 0x7C00.0000 8-CH DMA 0x7800.0000 EMI 0x7400.0000 USB 0x7000.0000 ENET 0x6C00.0000 8-CH DMA 0x6800.0000 EMI 0x6400.0000 USB 0x6000.0000 APB1 ...
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Electrical characteristics 6 Electrical characteristics 6.1 Absolute maximum ratings This product contains devices to protect the inputs against damage due to high static voltages. However advisable to take normal precautions to avoid application of any voltage higher than ...
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STR91xFA 6.2 Operating conditions Table 7. Operating conditions Symbol V Digital CPU supply voltage DD V Digital I/O supply voltage DDQ SRAM backup and RTC supply (1) V BATT voltage Analog ADC supply voltage AV DD (128-pin and 144-ball packages) ...
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Electrical characteristics 6.3 LVD electrical characteristics V = 2.7 - 3.6V, V DDQ Table 9. LVD Electrical Characteristics Symbol V (1.8V) LVD threshold during V DD_LVD+ V (1.8V) LVD threshold during V DD_LVD- V (1.8V) V brown out warning threshold ...
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STR91xFA Figure 11. LVD reset delay case (green (red) DDQ RESET_OUTn (blue) 6.4 DC electrical characteristics V = 2.7 - 3.6V, V DDQ Table 10. DC Electrical Characteristics Symbol Parameter V Input High Level IH ...
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Electrical characteristics 6.5 AC electrical characteristics V = 2.7 - 3.6V, V DDQ Table 11. AC electrical characteristics Symbol Parameter I Run Mode Current DDRUN I Idle Mode Current IDLE Sleep Mode Current, I SLEEP(IDD Sleep Mode Current, ...
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STR91xFA Figure 12. Sleep Mode current vs temperature with LVD on 2000 1800 1600 1400 1200 1000 800 600 400 200 -40 -20 Table 12. AC electrical characteristics Symbol Parameter f CCU Master Clk Output MSTR f CPU Core Frequency ...
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Electrical characteristics 6.6 RESET_INn and power-on-reset characteristics V = 2.7 - 3.6V, V DDQ Table 13. RESET_INn and Power-On-Reset Characteristics Symbol Parameter t RESET_INn Valid Active Low RINMIN Power-On-Reset Condition t POR duration RESET_OUT Duration t RSO (Watchdog reset) 1. ...
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STR91xFA Table 16. RTC crystal electrical characteristics Symbol Parameter f Resonant frequency O R Series resistance S C Load capacitance L 6.9 PLL electrical characteristics V = 2.7 - 3.6V, V DDQ Table 17. PLL Electrical Characteristics Symbol Parameter f ...
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Electrical characteristics 6.11 Flash memory characteristics V = 2.7 - 3.6V, V DDQ Table 19. Flash memory program/erase characteristics Parameter Primary Bank (512 Kbytes) Primary Bank Bank erase (256 Kbytes) Secondary Bank (32 Kbytes) Of Primary Bank (64 Kbytes) Sector ...
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STR91xFA 6.12 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 6.12.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed ...
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Electrical characteristics 6.12.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer ...
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... DLU Dynamic latch-up class Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). ...
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Electrical characteristics Symbol Parameter t Address to ALE hold time AAH t Address to ALE setup time (ALE_LENGTH AAS Notes: 1 ALE_LENGTH = 1 by default (can be programmed setting the bits In the ...
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STR91xFA Table 26. EMI write operation Symbol Parameter t WRn to CSn inactive WCR t Write Pulse Width WP Write Data Setup Time (non-mux mode) t WDS Write Data Setup Time (mux mode ) Write Data Hold t WDH Time ...
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Electrical characteristics Figure 15. Non-Mux Bus (8-bit) write timings EMI_CSxn EMI_A[15:0] EMI_D[7:0] EMI_BWR_WRLn Figure 16. Mux Bus (16-bit) Write Timings EMI_CSxn EMI_A LE EMI_A [23:16] EMI_A D[15:0] EMI_WRLn EMI_WRHn 62/78 Address Data tWAS tWDS ddress tA A ...
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STR91xFA 6.14 ADC electrical characteristics V = 2.7 - 3.6V, V DDQ Table 27. ADC electrical characteristics Symbol Parameter V Input Voltage Range AIN RES Resolution N Number of Input Channels CH f ADC Clock Frequency ADC t POR bit ...
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Electrical characteristics Figure 17. ADC conversion characteristics Digital Result 1023 1022 V V – DDA SSA 1LSB = ---------------------------------------- - IDEAL 1021 1024 LSB ...
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STR91xFA 6.15 Communication interface electrical characteristics 6.15.1 10/100 Ethernet MAC electrical characteristics V = 2.7 - 3.6V, V DDQ Ethernet MII Interface Timings Figure 18. MII_RX_CLK and MII_TX_CLK timing diagram MII_RX_TCLK, MII_TX_CLK Table 28. MII_RX_CLK and MII_TX_CLK timing table Symbol ...
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Electrical characteristics Table 30. Ethernet MII management timing table Symbol MDIO delay from rising 1 edge of MDC MDIO setup time to rising 2 edge of MDC MDIO hold time from rising 3 edge of MDC Ethernet MII transmit timings ...
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STR91xFA Ethernet MII Receive timings Figure 22. Ethernet MII receive timing diagram MII_RX_CLK MII_RXD MII_RX_DV MII_RX_ER Figure 23. Ethernet MII receive timing table Symbol MII_RXD valid to 1 MII_RX_CLK high MII_RX_CLK high to 2 MII_RXD invalid 6.15.2 USB electrical interface ...
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Electrical characteristics 2 6.15 electrical characteristics V = 2.7 - 3.6V, V DDQ 2 Table 32 Electrical Characteristics Symbol Bus free time between a STOP t BUF and START condition Hold time START condition. t After ...
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STR91xFA 6.15.5 SPI electrical characteristics V = 2.7 - 3.6V, V DDQ Table 33. SPI electrical characteristics Symbol f SCLK SPI clock frequency 1/t c(SCLK) t r(SCLK) SPI clock rise and fall times t f(SCLK setup time su(SS) ...
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Electrical characteristics Figure 25. SPI slave timing diagram with CPHA=1 NSS INPUT t su( NSS ) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t a(SO) MISO OUTPUT MOSI INPUT Figure 26. SPI master timing diagram NSS INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 CPHA=1 CPOL=0 ...
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STR91xFA 7 Package mechanical data Figure 27. 80-Pin Low Profile Quad Flat Package SEATING PLANE C ccc PIN 1 IDENTIFICATION 0.25 mm GAGE PLANE ...
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Package mechanical data Figure 28. 128-Pin Low Profile Quad Flat Package SEATING PLANE C ccc 128 1 e PIN 1 IDENTIFICATION 72/78 0.25 mm GAGE PLANE ...
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STR91xFA Figure 29. 144-Low Profile Fine Pitch Ball Grid Array Package Figure 30. Recommended PCB Design rules (0.80/0.75mm pitch BGA) Dpad Dsm Solder paste – Non solder mask defined pads are recommended – mils screen print Dpad ...
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Package mechanical data 7.1 Thermal characteristics The average chip-junction temperature, T The average chip-junction temperature, T following equation: x Θ Where: is the Ambient Temperature in °C, – Θ is ...
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... STR91xFA 8 Ordering information Table 35. Ordering information Part Number STR910FAM32X6 STR910FAW32X6 STR910FAZ32H6 STR911FAM42X6 STR911FAM44X6 STR911FAW42X6 STR911FAW44X6 STR912FAW34X6 STR912FAW42X6 STR912FAW44X6 STR912FAZ42H6 STR912FAZ44H6 Flash KB RAM KB Major Peripherals 256+32 64 256+32 64 CAN, EMI, 80 I/Os 256+32 64 CAN, EMI, 80 I/Os 256+32 96 USB, CAN, 40 I/Os 512+32 96 256+32 96 USB, CAN, EMI, 80 I/Os 512+32 96 512+32 ...
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Ordering information Table 36. Ordering information scheme Example: Family ARM9 Microcontroller Family Series 1 = STR9 Series 1 Feature set 0 = CAN, UART, IrDA, I2C, SSP 1 = USB, CAN, UART, IrDA, I2C, SSP 2 = USB, CAN, UART, ...
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STR91xFA 9 Revision history Table 37. Revision history Date Revision 09-May-2007 1 Initial release Revision history Changes 77/78 ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...