STR912FAW46X6T STMicroelectronics, STR912FAW46X6T Datasheet - Page 13

• Manufacturer Part Number: STR912FAW46X6T
• Description: MCU 16/32BIT FLASH 128-TQFP
• Manufacturer: STMicroelectronics
• Series: STR9r

Specifications of STR912FAW46X6T

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Processor Series: STR912x
• Core: ARM966E-S
• 3rd Party Development Tools: EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, KSDK-STR912-PLUS, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

STR91xFAxxx
3.4.2
3.4.3
Branch cache (BC)
When instruction addresses are not sequential, such as a program branch situation, the
PFQ would have to flush and reload which would cause the CPU to stall if no BC were
present. Before reloading, the PFQ checks the BC to see if it contains the desired target
branch address. The BC contains up to fifteen of the most recently taken branch addresses
and the first eight instructions associated with each of these branches. This check is
extremely fast, checking all fifteen BC entries simultaneously for a branch address match
(cache hit). If there is a hit, the BC rapidly supplies the instruction and reduces the CPU
stall. This gives the PFQ time to start pre-fetching again while the CPU consumes these
eight instructions from the BC. The advantage here is that program loops (very common
with embedded control applications) run very fast if the address of the loops are contained
in the BC.
In addition, there is a 16th branch cache entry that is dedicated to the Vectored Interrupt
Controller (VIC) to further reduce interrupt latency by eliminating the stall latency typically
imposed by fetching the instruction that reads the interrupt vector address from the VIC.
Management of literals
Typical ARM architecture and compilers do not place literals (data constants) sequentially in
Flash memory with the instructions that use them, but instead the literals are placed at some
other address which looks like a program branch from the PFQ’s point of view. The
STR91xFA implementation of the ARM966E-S core has special circuitry to prevent flushing
the PFQ when literals are encountered in program flow to keep performance at a maximum.
Doc ID 13495 Rev 6
Functional overview
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