ST10F276-4T3 STMicroelectronics, ST10F276-4T3 Datasheet - Page 122

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ST10F276-4T3

Manufacturer Part Number
ST10F276-4T3
Description
MCU 16BIT 832K FLASH 144-LQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of ST10F276-4T3

Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
832KB (832K x 8)
Program Memory Type
FLASH
Ram Size
68K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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0
System reset
122/231
To ensure correct power-up reset with controlled supply current consumption, specially if
clock signal requires a long period of time to stabilize, an asynchronous hardware reset is
required during power-up. For this reason, it is recommended to connect the external R0-C0
circuit shown in
forces an asynchronous hardware reset when RSTIN is asserted low. The external pull-up
R0 will then charge the capacitor C0. Note that an internal pull-down device on RPD pin is
turned on when RSTIN pin is low, and causes the external capacitor (C0) to begin
discharging at a typical rate of 100-200µA. With this mechanism, after power-up reset, short
low pulses applied on RSTIN produce synchronous hardware reset. If RSTIN is asserted
longer than the time needed for C0 to be discharged by the internal pull-down device, then
the device is forced in an asynchronous reset. This mechanism insures recovery from very
catastrophic failure.
Figure 37. Minimum external reset circuitry
The minimum reset circuit of
the ST10F276E itself during software or watchdog triggered resets, because of the
capacitor C1 that will keep the voltage on RSTIN pin above V
reset sequence, and thus will trigger an asynchronous reset sequence.
Figure 38
used to generate power-up or manual reset, and R0-C0 circuit on RPD is used for power-up
reset and to exit from Power Down mode. Diode D1 creates a wired-OR gate connection to
the reset pin and may be replaced by open-collector Schmitt trigger buffer. Diode D2
provides a faster cycle time for repetitive power-on resets.
R2 is an optional pull-up for faster recovery and correct biasing of TTL Open Collector
drivers.
shows an example of a reset circuit. In this example, R1-C1 external circuit is only
Figure 37
to the RPD pin. On power-up, the logical low level on RPD pin
ST10F276
Figure 37
RSTOUT
RSTIN
RPD
is not adequate when the RSTIN pin is driven from
+
+
V
CC
R0
C0
C1
External Hardware
(and Interruptible
Power Down
mode)
b) For Power-up
Reset
a) Hardware
Reset
IL
after the end of the internal
ST10F276E

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