MC908QY2CDTER Freescale Semiconductor, MC908QY2CDTER Datasheet - Page 53

• Manufacturer Part Number: MC908QY2CDTER
• Description: IC MCU 8BIT 1.5K FLASH 16TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QY2CDTER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

Chapter 5
Configuration Register (CONFIG)
5.1 Introduction
This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers
enable or disable the following options:
5.2 Functional Description
The configuration registers are used in the initialization of various options. The configuration registers can
be written once after each reset. Most of the configuration register bits are cleared during reset. Since the
various options affect the operation of the microcontroller unit (MCU) it is recommended that this register
be written immediately after reset. The configuration registers are located at $001E and $001F, and may
be read at anytime.
Freescale Semiconductor
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Stop mode recovery time (32 × BUSCLKX4 cycles or
4096 × BUSCLKX4 cycles)
STOP instruction
Computer operating properly module (COP)
COP reset period (COPRS): 8176 × BUSCLKX4 or 262,128 × BUSCLKX4
Low-voltage inhibit (LVI) enable and trip voltage selection
OSC option selection
IRQ pin
RST pin
Auto wakeup timeout period
Address: $001E
The CONFIG registers are one-time writable by the user after each reset.
Upon a reset, the CONFIG registers default to predetermined settings as
shown in
Reset:
Read:
Write:
POR:
IRQPUD
Bit 7
R
0
0
Figure 5-1
Figure 5-1. Configuration Register 2 (CONFIG2)
= Reserved
IRQEN
MC68HC908QY/QT Family Data Sheet, Rev. 6
6
0
0
and
Figure
R
5
0
0
5-2.
U = Unaffected
OSCOPT1
NOTE
4
0
0
OSCOPT0
3
0
0
R
2
0
0
R
1
0
0
RSTEN
Bit 0
U
0
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