MC9S08SV8CLC Freescale Semiconductor, MC9S08SV8CLC Datasheet - Page 22

• Manufacturer Part Number: MC9S08SV8CLC
• Description: MCU 8BIT 8K FLASH 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08SV8CLC

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: S08SV
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 30
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08SV16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2
3
4
5
6
7
Electrical Characteristics
22
When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz
to 39.0625 kHz.
See crystal or resonator manufacturer’s recommendation.
This parameter is characterized and not tested on each device.
Proper PC board layout procedures must be followed to achieve specifications.
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, DMX32 bit
is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a
crystal/resonator is being used as the reference, this specification assumes it is already running.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V
given interval.
Figure 16. Deviation of DCO Output from Trimmed Frequency (20 MHz, 5.0 V)
-60
Figure 15. Typical Crystal or Resonator Circuit
DD
-40
and V
C
1
EXTAL
MC9S08SV16 Series Data Sheet, Rev. 2
-20
SS
-0.50%
-1.00%
-1.50%
-2.00%
1.00%
0.50%
0.00%
and variation in crystal oscillator frequency increase the C
0
Crystal or Resonator
TBD
XOSC
Temperature
20
R
F
40
60
XTAL
R
80
S
C
2
100
120
Freescale Semiconductor
Jitter
percentage for a
Bus
.