S9S08SG16E1VTJ Freescale Semiconductor, S9S08SG16E1VTJ Datasheet - Page 156

• Manufacturer Part Number: S9S08SG16E1VTJ
• Description: MCU 16K FLASH 20-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08SG16E1VTJ

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-TSSOP
• Processor Series: S08SG
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: - 0.3 V to + 5.8 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• On-chip Dac: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 10 Inter-Integrated Circuit (S08IICV2)
For example, if the bus speed is 8 MHz, the table below shows the possible hold time values with different
ICR and MULT selections to achieve an IIC baud rate of 100kbps.
156
MULT
Field
ICR
7–6
5–0
IIC Multiplier Factor. The MULT bits define the multiplier factor, mul. This factor, along with the SCL divider,
generates the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below.
00 mul = 01
01 mul = 02
10 mul = 04
11 Reserved
IIC Clock Rate. The ICR bits are used to prescale the bus clock for bit rate selection. These bits and the MULT
bits determine the IIC baud rate, the SDA hold time, the SCL Start hold time, and the SCL Stop hold time.
Table 10-5
The SCL divider multiplied by multiplier factor mul generates IIC baud rate.
SDA hold time is the delay from the falling edge of SCL (IIC clock) to the changing of SDA (IIC data).
SCL start hold time is the delay from the falling edge of SDA (IIC data) while SCL is high (Start condition) to the
falling edge of SCL (IIC clock).
SCL stop hold time is the delay from the rising edge of SCL (IIC clock) to the rising edge of SDA
SDA (IIC data) while SCL is high (Stop condition).
MULT
0x2
0x1
0x1
0x0
0x0
provides the SCL divider and hold values for corresponding values of the ICR.
SCL Start hold time = bus period (s)
SCL Stop hold time = bus period (s)
Table 10-4. Hold Time Values for 8 MHz Bus Speed
SDA hold time = bus period (s)
Table 10-3. IICF Field Descriptions
0x0B
0x00
0x07
0x14
0x18
ICR
MC9S08SG32 Data Sheet, Rev. 8
IIC baud rate
3.500
2.500
2.250
2.125
1.125
SDA
=
Description
-------------------------------------------- -
mul SCLdivider
bus speed (Hz)
×
×
×
×
mul
mul
mul
Hold Times (μs)
×
×
×
SCL Start
SDA hold value
SCL Start hold value
SCL Stop hold value
3.000
4.000
4.000
4.250
4.750
SCL Stop
5.500
5.250
5.250
5.125
5.125
Freescale Semiconductor
Eqn. 10-1
Eqn. 10-2
Eqn. 10-3
Eqn. 10-4