MC9S08QG8MPBE Freescale Semiconductor, MC9S08QG8MPBE Datasheet - Page 215
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MC9S08QG8MPBE
Manufacturer Part Number
MC9S08QG8MPBE
Description
IC MCU 8K FLASH 16-PDIP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08QG8CDTER.pdf
(314 pages)
Specifications of MC9S08QG8MPBE
Core Processor
HCS08
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-DIP (0.300", 7.62mm)
Processor Series
S08QG
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI/SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
1
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08QG8E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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15.1.1
Features of the SPI module include:
15.1.2
This section includes block diagrams showing SPI system connections, the internal organization of the SPI
module, and the SPI clock dividers that control the master mode bit rate.
15.1.2.1
Figure 15-2
device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the
slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively
exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock
output from the master and an input to the slave. The slave device must be selected by a low level on the
slave select input (SS pin). In this system, the master device has configured its SS pin as an optional slave
select output.
Freescale Semiconductor
•
•
•
•
•
•
•
Master or slave mode operation
Full-duplex or single-wire bidirectional option
Programmable transmit bit rate
Double-buffered transmit and receive
Serial clock phase and polarity options
Slave select output
Selectable MSB-first or LSB-first shifting
7
6
Features
Block Diagrams
shows the SPI modules of two MCUs connected in a master-slave arrangement. The master
SPI System Block Diagram
5
GENERATOR
SPI SHIFTER
MASTER
CLOCK
4
3
2
1
0
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Figure 15-2. SPI System Connections
MOSI
MISO
SPSCK
SS
SPSCK
MOSI
MISO
SS
7
SLAVE
6
5
SPI SHIFTER
4
Serial Peripheral Interface (S08SPIV3)
3
2
1
0
213
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