MC9S08SH32CWL Freescale Semiconductor, MC9S08SH32CWL Datasheet - Page 80
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MC9S08SH32CWL
Manufacturer Part Number
MC9S08SH32CWL
Description
MCU 8BIT 32K FLASH 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08SH32CWL
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
S08SH
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO, DEMO9S08SH32, DEMO9S08SH8
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S08SH32CWL
Manufacturer:
FREESCALE
Quantity:
20 000
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1
Chapter 6 Parallel Input/Output Control
6.6.1
Port A is controlled by the registers listed below.
The pins PTA4 and PTA5 are unique. PTA4 is output-only, so the control bits for the input function will
not have any effect on this pin. PTA5, when configured as an output, is open drain with low drive strength.
6.6.1.1
80
PTAD[5:0]
Reset:
Reads of bit PTAD4 always return the contents of PTAD4, regardless of the value stored in bit PTADD4.
Field
5:0
W
R
Port A Registers
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
Port A Data Register (PTAD)
0
0
7
This PTA5 pin does not contain a clamp diode to V
driven above V
When the internal pullup device is enabled on PTA5 when used as an input
or open drain output the voltage measured on PTA5 will not be pulled to
V
pin is required to drive to a V
DD
. The internal gates connected to this pin are pulled to V
0
0
6
DD
Table 6-2. PTAD Register Field Descriptions
.
Figure 6-3. Port A Data Register (PTAD)
MC9S08SH8 MCU Series Data Sheet, Rev. 3
PTAD5
0
5
DD
PTAD4
level an external pullup should be used.
NOTE
0
4
1
Description
PTAD3
3
0
DD
and should not be
PTAD2
DD
0
2
. If the PTA5
Freescale Semiconductor
PTAD1
0
1
PTAD0
0
0
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