MC908QB8MDTE Freescale Semiconductor, MC908QB8MDTE Datasheet - Page 193
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MC908QB8MDTE
Manufacturer Part Number
MC908QB8MDTE
Description
IC MCU 8BIT 8K FLASH 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908QB8CDWE.pdf
(236 pages)
Specifications of MC908QB8MDTE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-TSSOP
Processor Series
HC08QB
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
3-Wire, ESCI, SPI, UART
Number Of Programmable I/os
13
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Controller Family/series
HC08
No. Of I/o's
14
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
1
Digital Ic Case Style
TSSOP
Rohs Compliant
Yes
For Use With
DEMO908QB8 - BOARD DEMO FOR MC68HC908QB8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908QB8MDTE
Manufacturer:
MAX
Quantity:
150
Part Number:
MC908QB8MDTE
Manufacturer:
FREESCALE
Quantity:
20 000
The break interrupt timing is:
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can
be generated continuously.
17.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See
for each module.
17.2.1.2 TIM During Break Interrupts
A break interrupt stops the timer counter.
17.2.1.3 COP During Break Interrupts
The COP is disabled during a break interrupt in monitor mode when the BDCOP bit is set in the break
auxiliary register (BRKAR).
Freescale Semiconductor
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•
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When a break address is placed at the address of the instruction opcode, the instruction is not
executed until after completion of the break interrupt routine.
When a break address is placed at an address of an instruction operand, the instruction is executed
before the break interrupt.
When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction
is executed.
ADDRESS BUS[15:0]
A break address should be placed at the address of the instruction opcode.
When software does not change the break address and clears the BRKA
bit in the first break interrupt routine, the next break interrupt will not be
generated after exiting the interrupt routine even when the internal address
bus matches the value written in the break address registers.
Figure 17-2. Break Module Block Diagram
ADDRESS BUS[15:8]
ADDRESS BUS[7:0]
14.8.2 Break Flag Control Register
MC68HC908QB8 Data Sheet, Rev. 3
BREAK ADDRESS REGISTER HIGH
BREAK ADDRESS REGISTER LOW
8-BIT COMPARATOR
8-BIT COMPARATOR
CAUTION
and the Break Interrupts subsection
CONTROL
BKPT
(TO SIM)
Break Module (BRK)
193