C8051F331-GMR Silicon Laboratories Inc, C8051F331-GMR Datasheet - Page 109

• Manufacturer Part Number: C8051F331-GMR
• Description: IC 8051 MCU 8K FLASH 20QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F331-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• For Use With: 336-1451 - ADAPTER PROGRAM TOOLSTICK F330336-1264 - DEV KIT FOR C8051F330/F331
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

13. Oscillators
C8051F330/1/2/3/4/5 devices include a programmable internal high-frequency oscillator, a programmable
internal low-frequency oscillator, and an external oscillator drive circuit. The internal high-frequency oscilla-
tor can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in
Figure 13.1. The internal low-frequency oscillator can be enabled/disabled and calibrated using the
OSCLCN register, as shown in SFR Definition 13.3. The system clock can be sourced by the external
oscillator circuit or either internal oscillator. Both internal oscillators offer a selectable post-scaling feature.
The internal oscillators’ electrical specifications are given in Table 13.1 on page 122.
13.1. Programmable Internal High-Frequency (H-F) Oscillator
All C8051F330/1/2/3/4/5 devices include a programmable internal high-frequency oscillator that defaults
as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL
register as defined by SFR Definition 13.1.
On C8051F330/1/2/3/4/5 devices, OSCICL is factory calibrated to obtain a 24.5 MHz base frequency.
Electrical specifications for the precision internal oscillator are given in Table 13.1 on page 122. Note that
the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as
defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset.
VDD
Option 2
Option 3
XTAL2
XTAL2
Option 1
Option 4
XTAL2
10M
Figure 13.1. Oscillator Diagram
XTAL1
XTAL2
OSCICL
Rev. 1.7
Circuit
OSCLF
Low Frequency
Input
Programmable
Internal Clock
Generator
OSCXCN
Oscillator
OSC
EN
EN
OSCICN
C8051F330/1/2/3/4/5
OSCLD
n
n
CLKSEL
OSCLCN
OSCLF OSCLD
SYSCLK
113