S9S08AW60E5MFDE Freescale Semiconductor, S9S08AW60E5MFDE Datasheet - Page 226
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S9S08AW60E5MFDE
Manufacturer Part Number
S9S08AW60E5MFDE
Description
MCU 64K FLASH AUTO MONET 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08AW32CFDE.pdf
(324 pages)
Specifications of S9S08AW60E5MFDE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Controller Family/series
HCS08
No. Of I/o's
38
Ram Memory Size
2KB
Cpu Speed
40MHz
No. Of Timers
2
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Chapter 13 Inter-Integrated Circuit (S08IICV1)
13.4.1.1
When the bus is free; i.e., no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal. As shown in
START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the
beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves
out of their idle states.
13.4.1.2
The first byte of data transferred immediately after the START signal is the slave address transmitted by
the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
Only the slave with a calling address that matches the one transmitted by the master will respond by
sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see
No two slaves in the system may have the same address. If the IIC module is the master, it must not transmit
an address that is equal to its own slave address. The IIC cannot be master and slave at the same time.
However, if arbitration is lost during an address cycle, the IIC will revert to slave mode and operate
correctly even if it is being addressed by another master.
13.4.1.3
Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction
specified by the R/W bit sent by the calling master.
All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address
information for the slave device
Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while
SCL is high as shown in
transferred first. Each data byte is followed by a 9th (acknowledge) bit, which is signalled from the
receiving device. An acknowledge is signalled by pulling the SDA low at the ninth clock. In summary, one
complete data transfer needs nine clock pulses.
If the slave receiver does not acknowledge the master in the 9th bit time, the SDA line must be left high
by the slave. The master interprets the failed acknowledge as an unsuccessful data transfer.
If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave
interprets this as an end of data transfer and releases the SDA line.
In either case, the data transfer is aborted and the master does one of two things:
226
•
•
1 = Read transfer, the slave transmits data to the master.
0 = Write transfer, the master transmits data to the slave.
Relinquishes the bus by generating a STOP signal.
Commences a new calling by generating a repeated START signal.
START Signal
Slave Address Transmission
Data Transfer
Figure
13-8. There is one clock pulse on SCL for each data bit, the MSB being
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
Figure
Figure
13-8, a
13-8).
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