C8051F338-GMR Silicon Laboratories Inc, C8051F338-GMR Datasheet - Page 105

• Manufacturer Part Number: C8051F338-GMR
• Description: IC MCU 16K FLASH 24QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F338-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-QFN
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F336DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 10 bit
• Height: 0.73 mm
• Length: 4 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 4 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: Q4962654; T1084322

SFR Definition 17.2. RSTSRC: Reset Source
SFR Address = 0xEF
Note: Do not use read-modify-write operations on this register
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
WDTRSF Watchdog Timer Reset Flag. N/A
MCDRSF Missing Clock Detector
UNUSED Unused.
FERROR Flash Error Reset Flag.
C0RSEF Comparator0 Reset Enable
PINRSF
SWRSF
PORSF
Name
R
7
0
and Flag.
Software Reset Force and
Flag.
Enable and Flag.
Power-On / V
Reset Flag, and V
Reset Enable.
HW Pin Reset Flag.
FERROR
Varies
R
6
Description
DD
C0RSEF
Varies
Monitor
R/W
DD
5
monitor
SWRSF
Varies
R/W
Rev.1.0
Don’t care.
N/A
Writing a ‘1’ enables
Comparator0 as a reset
source (active-low).
Writing a ‘1’ forces a sys-
tem reset.
Writing a ‘1’ enables the
Missing Clock Detector.
The MCD triggers a reset
if a missing clock condition
is detected.
Writing a ‘1’ enables the
V
source.
Writing ‘1’ to this bit
before the V
is enabled and stabilized
may cause a system
reset.
N/A
4
DD
monitor as a reset
WDTRSF
Varies
Write
R
3
DD
monitor
MCDRSF
C8051F336/7/8/9
Varies
R/W
2
0
Set to ‘1’ if Flash
read/write/erase error
caused the last reset.
Set to ‘1’ if Comparator0
caused the last reset.
Set to ‘1’ if last reset was
caused by a write to
SWRSF.
Set to ‘1’ if Watchdog
Timer overflow caused the
last reset.
Set to ‘1’ if Missing Clock
Detector timeout caused
the last reset.
Set to ‘1’ anytime a power-
on or V
occurs.
When set to ‘1’ all other
RSTSRC flags are inde-
terminate.
Set to ‘1’ if RST pin
caused the last reset.
PORSF
Varies
R/W
DD
1
Read
monitor reset
PINRSF
Varies
R
0
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