C8051F338-GMR Silicon Laboratories Inc, C8051F338-GMR Datasheet - Page 43

• Manufacturer Part Number: C8051F338-GMR
• Description: IC MCU 16K FLASH 24QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F338-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-QFN
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F336DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 10 bit
• Height: 0.73 mm
• Length: 4 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 4 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: Q4962654; T1084322

SFR Definition 7.4. ADC0CN: ADC0 Control
SFR Address = 0xE8; Bit-Addressable
Name
Reset
Bit
2:0 AD0CM[2:0] ADC0 Start of Conversion Mode Select.
Type
7
6
5
4
3
Bit
AD0BUSY ADC0 Busy Bit.
AD0WINT
AD0INT
AD0EN
AD0TM
Name
AD0EN
R/W
7
0
ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a con-
version is in progress. Conversion begins immediately on start-of-conversion event,
as defined by AD0CM[2:0].
1: Low-power Track Mode: For AD0CM[2:0] = 100, ADC is tracking when CNVSTR is
low, and conversion begins immediately on rising edge of CNVSTR.
For all other values of AD0CM[2:0], tracking is initiated on start-of-conversion event,
and lasts 3 SAR Clock cycles. The conversion immediately follows this tracking
phase.
ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since AD0INT was last cleared.
1: ADC0 has completed a data conversion.
ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match has not occurred since this flag was last
cleared.
1: ADC0 Window Comparison Data match has occurred.
000: ADC0 start-of-conversion source is write of ‘1’ to AD0BUSY.
001: ADC0 start-of-conversion source is overflow of Timer 0.
010: ADC0 start-of-conversion source is overflow of Timer 2.
011: ADC0 start-of-conversion source is overflow of Timer 1.
100: ADC0 start-of-conversion source is rising edge of external CNVSTR.
101: ADC0 start-of-conversion source is overflow of Timer 3.
11x: Reserved.
AD0TM
R/W
6
0
AD0INT
R/W
5
0
AD0BUSY AD0WINT
R/W
Rev.1.0
4
0
Read:
0: ADC0 conversion is not
in progress.
1: ADC0 conversion is in
progress.
Function
R/W
3
0
C8051F336/7/8/9
2
0
Write:
0: No Effect.
1: Initiates ADC0 Conver-
sion if AD0CM[2:0] =
000b
AD0CM[2:0]
R/W
1
0
0
0
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