MC9S08DZ48ACLF Freescale Semiconductor, MC9S08DZ48ACLF Datasheet - Page 191
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MC9S08DZ48ACLF
Manufacturer Part Number
MC9S08DZ48ACLF
Description
IC MCU 48K FLASH 3K RAM 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DZ48ACLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Eeprom Size
1.5K x 8
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
EVB9S08DZ60 - BOARD EVAL FOR 9S08DZ60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ48ACLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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The maximum total conversion time is determined by the clock source chosen and the divide ratio selected.
The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For
example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1
ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is:
10.4.5
The compare function can be configured to check for an upper or lower limit. After the input is sampled
and converted, the result is added to the two’s complement of the compare value (ADCCVH and
ADCCVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to the
compare value, COCO is set. When comparing to a lower limit (ACFGT = 0), if the result is less than the
compare value, COCO is set. The value generated by the addition of the conversion result and the two’s
complement of the compare value is transferred to ADCRH and ADCRL.
Upon completion of a conversion while the compare function is enabled, if the compare condition is not
true, COCO is not set and no data is transferred to the result registers. An ADC interrupt is generated upon
the setting of COCO if the ADC interrupt is enabled (AIEN = 1).
10.4.6
Wait mode is a lower power-consumption standby mode from which recovery is fast because the clock
sources remain active. If a conversion is in progress when the MCU enters wait mode, it continues until
completion. Conversions can be initiated while the MCU is in wait mode by means of the hardware trigger
or if continuous conversions are enabled.
The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in
wait mode. The use of ALTCLK as the conversion clock source in wait is dependent on the definition of
Freescale Semiconductor
Subsequent continuous 10-bit or 12-bit;
Automatic Compare Function
MCU Wait Mode Operation
Conversion Type
f
BUS
The ADCK frequency must be between f
maximum to meet ADC specifications.
The compare function can monitor the voltage on a channel while the MCU
is in wait or stop3 mode. The ADC interrupt wakes the MCU when the
compare condition is met.
> f
ADCK
Conversion time =
Table 10-13. Total Conversion Time vs. Control Conditions
/11
Number of bus cycles = 3.5 ms x 8 MHz = 28 cycles
MC9S08DZ60 Series Data Sheet, Rev. 4
23 ADCK Cyc
8 MHz/1
ADICLK
xx
NOTE
NOTE
ADLSMP
ADCK
+
1
Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
5 bus Cyc
minimum and f
8 MHz
Max Total Conversion Time
= 3.5 ms
ADCK
40 ADCK cycles
191
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