MC9S08RE16CFDER Freescale Semiconductor, MC9S08RE16CFDER Datasheet - Page 173
![IC MCU 16K FLASH 1K RAM 48-QFN](/photos/37/62/376240/qfn-48_sml.jpg)
MC9S08RE16CFDER
Manufacturer Part Number
MC9S08RE16CFDER
Description
IC MCU 16K FLASH 1K RAM 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08RE16CFDER
Core Processor
HCS08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
S08RE
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
39
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08RG60E
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (2Mb)
SSOE — Slave Select Output Enable
LSBFE — LSB First (Shifter Direction)
13.4.2
This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not
implemented and always read 0.
MODFEN — Master Mode-Fault Function Enable
Freescale Semiconductor
This bit is used in combination with the mode fault enable (MODFEN) bit in SPCR2 and the
master/slave (MSTR) control bit to determine the function of the SS1 pin as shown in
When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS1 pin is the slave
select input.) In master mode, this bit determines how the SS1 pin is used (refer to
details).
1 = SPI serial data transfers start with least significant bit.
0 = SPI serial data transfers start with most significant bit.
1 = Mode fault function enabled, master SS1 pin acts as the mode fault input or the slave select
0 = Mode fault function disabled, master SS1 pin reverts to general-purpose I/O not controlled by
output.
SPI.
SPI Control Register 2 (SPI1C2)
MODFEN
0
0
1
1
Reset:
Read:
Write:
SSOE
0
1
0
1
Bit 7
Figure 13-8. SPI Control Register 2 (SPI1C2)
0
0
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
General-purpose I/O (not SPI)
General-purpose I/O (not SPI)
SS input for mode fault
Automatic SS output
= Unimplemented or Reserved
Table 13-1. SS1 Pin Function
6
0
0
Master Mode
5
0
0
MODFEN
<st-blue>
4
0
<st-blue>
BIDIROE
Slave select input
Slave select input
Slave select input
Slave select input
3
0
Slave Mode
Serial Peripheral Interface (SPI) Module
2
0
0
<st-blue>
SPISWAI
Table 13-1
1
0
Table
<st-blue>
SPC0
Bit 0
0
for more
13-1.
173
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