S9S08DZ60F1MLF Freescale Semiconductor, S9S08DZ60F1MLF Datasheet - Page 372
S9S08DZ60F1MLF
Manufacturer Part Number
S9S08DZ60F1MLF
Description
MCU 60K FLASH MASK AUTO 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.DEMO9S08DZ60.pdf
(416 pages)
Specifications of S9S08DZ60F1MLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S08DZ60F1MLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
S9S08DZ60F1MLF
Manufacturer:
FREESCALE
Quantity:
20 000
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Appendix A Electrical Characteristics
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring
P
solving equations 1 and 2 iteratively for any value of T
A.5
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM) and the Charge Device Model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
372
D
(at equilibrium) for a known T
Num
Human Body
Latch-up
1
2
3
ESD Protection and Latch-Up Immunity
Model
Human Body Model (HBM)
Charge Device Model (CDM)
Latch-up Current at T
Series Resistance
Storage Capacitance
Number of Pulse per pin
Minimum input voltage limit
Maximum input voltage limit
Table A-5. ESD and Latch-Up Protection Characteristics
Table A-4. ESD and Latch-up Test Conditions
A
= 125°C
Rating
A
. Using this value of K, the values of P
MC9S08DZ60 Series Data Sheet, Rev. 4
Description
A
.
Symbol
V
V
I
HBM
CDM
LAT
Symbol
+/- 2000
+/- 500
+/- 100
R1
C
–
Min
D
and T
J
Value
1500
–2.5
100
can be obtained by
7.5
Max
3
Freescale Semiconductor
–
–
–
Unit
pF
Ω
Unit
mA
V
V
V
V
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