MC9S08AW32CFGE Freescale Semiconductor, MC9S08AW32CFGE Datasheet - Page 79
![IC MCU 32K FLASH 44-LQFP](/photos/12/35/123573/mc9s08aw16mfge_sml.jpg)
MC9S08AW32CFGE
Manufacturer Part Number
MC9S08AW32CFGE
Description
IC MCU 32K FLASH 44-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08AW32CFGE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
S08AW
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
34
Number Of Timers
8
Operating Supply Voltage
- 0.3 V to + 5.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AW60E
Minimum Operating Temperature
- 55 C
On-chip Adc
10 bit, 8 Channel
Package
44LQFP
Family Name
HCS08
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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1
2
5.9.8
Freescale Semiconductor
Bit 1 is a reserved bit that must always be written to 0.
This bit can be written only one time after reset. Additional writes are ignored.
LVDACK
Reset
LVDRE
LVDSE
LVDIE
BGBE
LVDE
Field
LVDF
7
6
5
4
3
2
0
W
R
System Power Management Status and Control 1 Register (SPMSC1)
LVDF
Figure 5-10. System Power Management Status and Control 1 Register (SPMSC1)
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return 0.
Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
Bandgap Buffer Enable — The BGBE bit is used to enable an internal buffer for the bandgap voltage reference
for use by the ADC module on one of its internal channels.
0 Bandgap buffer disabled.
1 Bandgap buffer enabled.
0
7
= Unimplemented or Reserved
LVDACK
0
0
6
Table 5-11. SPMSC1 Register Field Descriptions
LVDIE
0
5
MC9S08AW60 Data Sheet, Rev 2
LVDRE
1
4
(2)
Description
LVDSE
Chapter 5 Resets, Interrupts, and System Configuration
3
1
(2)
LVDE
1
2
(2)
1
0
1
BGBE
0
0
79
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