S9S08DZ128F2MLF Freescale Semiconductor, S9S08DZ128F2MLF Datasheet - Page 393
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S9S08DZ128F2MLF
Manufacturer Part Number
S9S08DZ128F2MLF
Description
MCU 128K FLASH AUTO 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08DV96CLF.pdf
(458 pages)
Specifications of S9S08DZ128F2MLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S08D
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
87
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S08DZ128F2MLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 18
Debug Module (S08DBGV3)
18.1
The DBG module implements an on-chip ICE (in-circuit emulation) system and allows non-intrusive
debug of application software by providing an on-chip trace buffer with flexible triggering capability. The
trigger also can provide extended breakpoint capacity. The on-chip ICE system is optimized for the HCS08
8-bit architecture and supports 64K bytes or 128K bytes of memory space.
18.1.1
The on-chip ICE system includes these distinctive features:
Freescale Semiconductor
•
•
•
•
Three comparators (A, B, and C) with ability to match addresses in 128K space
— Dual mode, Comparators A and B used to compare addresses
— Full mode, Comparator A compares address and Comparator B compares data
— Can be used as triggers and/or breakpoints
— Comparator C can be used as a normal hardware breakpoint
— Loop1 capture mode, Comparator C is used to track most recent COF event captured into FIFO
Tag and Force type breakpoints
Nine trigger modes
— A
— A Or B
— A Then B
— A And B, where B is data (Full mode)
— A And Not B, where B is data (Full mode)
— Event Only B, store data
— A Then Event Only B, store data
— Inside Range, A ≤ Address ≤ B
— Outside Range, Address < Α or Address > B
FIFO for storing change of flow information and event only data
— Source address of conditional branches taken
— Destination address of indirect JMP and JSR instruction
— Destination address of interrupts, RTI, RTC, and RTS instruction
— Data associated with Event B trigger modes
Introduction
Features
MC9S08DZ128 Series Data Sheet, Rev. 1
(128K)
393
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