MC908LJ12CFUER Freescale Semiconductor, MC908LJ12CFUER Datasheet - Page 389
MC908LJ12CFUER
Manufacturer Part Number
MC908LJ12CFUER
Description
IC MCU 12K FLASH 4/8MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68HC98LJ12CFUE.pdf
(414 pages)
Specifications of MC908LJ12CFUER
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908LJ12CFUER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MC68HC908LJ12
Freescale Semiconductor
;
;
;
;
This code works if the H register has been pushed onto the stack in the break
service routine software. This code should be executed at the end of the break
service routine software.
HIBYTE
LOBYTE
DOLO
RETURN
EQU
EQU
If not SBSW, do RTI
BRCLR
TST
BNE
DEC
DEC
PULH
RTI
—
Rev. 2.1
5
6
SBSW,SBSR, RETURN
LOBYTE,SP
DOLO
HIBYTE,SP
LOBYTE,SP
Note: Writing a logic 0 clears SBSW.
Address:
SBSW — Break Wait Bit
SBSW can be read within the break interrupt routine. The user can
modify the return address on the stack by subtracting 1 from it. The
following code is an example.
Reset:
Read:
Write:
This status bit is set when a break interrupt causes an exit from wait
mode or stop mode. Clear SBSW by writing a logic 0 to it. Reset clears
SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
$FE00
Bit 7
R
Figure 22-6. SIM Break Status Register (SBSR)
Break Module (BRK)
R
6
;
;
;If RETURNLO is not zero,
;then just decrement low byte.
;Else deal with high byte, too.
;Point to WAIT/STOP opcode.
;Restore H register.
See if wait mode or stop mode was exited by
break.
R
R
5
= Reserved
R
4
R
3
R
2
Break Module (BRK)
SBSW
Note
1
0
Technical Data
Bit 0
R
389
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