C8051F351-GMR Silicon Laboratories Inc, C8051F351-GMR Datasheet - Page 127
C8051F351-GMR
Manufacturer Part Number
C8051F351-GMR
Description
IC 8051 MCU 8K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F35xr
Specifications of C8051F351-GMR
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x24b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F350DK
Minimum Operating Temperature
- 40 C
On-chip Adc
24 bit, 8 Channel
On-chip Dac
8 bit, 2 Channel
For Use With
336-1083 - DEV KIT FOR F350/351/352/353
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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16. External RAM
The C8051F350/1/2/3 devices include 512 bytes of RAM mapped into the external data memory space. All
of these address locations may be accessed using the external move instruction (MOVX) and the data
pointer (DPTR), or using MOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit
address operand (such as @R1), then the high byte of the 16-bit address is provided by the External Mem-
ory Interface Control Register (EMI0CN as shown in SFR Definition 16.1). Note: the MOVX instruction is
also used for writes to the Flash memory. See Section “15. Flash Memory’ on page 121 for details. The
MOVX instruction accesses XRAM by default.
For a 16-bit MOVX operation (@DPTR), the upper 7-bits of the 16-bit external data memory address word
are "don't cares". As a result, the 512-byte RAM is mapped modulo style over the entire 64 k external data
memory address range. For example, the XRAM byte at address 0x0000 is shadowed at addresses
0x0200, 0x0400, 0x0600, 0x0800, etc. This is a useful feature when performing a linear memory fill, as the
address pointer doesn't have to be reset when reaching the RAM block boundary.
Bits 7–1: UNUSED. Read = 0000000b. Write = don’t care.
Bit 0:
R/W
Bit7
—
SFR Definition 16.1. EMI0CN: External Memory Interface Control
PGSEL: XRAM Page Select.
The EMI0CN register provides the high byte of the 16-bit external data memory address
when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. Since
the upper (unused) bits of the register are always zero, the PGSEL determines which page
of XRAM is accessed.
For Example: If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be accessed.
R/W
Bit6
—
R/W
Bit5
—
R/W
Bit4
—
Rev. 1.1
R/W
Bit3
—
R/W
Bit2
—
C8051F350/1/2/3
R/W
Bit1
—
SFR Address:
PGSEL
R/W
Bit0
0xAA
00000000
Reset Value
127
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