C8051F351-GMR Silicon Laboratories Inc, C8051F351-GMR Datasheet - Page 26

• Manufacturer Part Number: C8051F351-GMR
• Description: IC 8051 MCU 8K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F351-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x24b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F350DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 24 bit, 8 Channel
• On-chip Dac: 8 bit, 2 Channel
• For Use With: 336-1083 - DEV KIT FOR F350/351/352/353
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F350/1/2/3
1.6.
C8051F350/1/2/3 devices include a software-configurable voltage comparator with an input multiplexer.
The Comparator offers programmable response time and hysteresis and two outputs that are optionally
available at the Port pins: a synchronous “latched” output (CP0), or an asynchronous “raw” output (CP0A).
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these inter-
rupts may be used as a “wake-up” source for the processor. Comparator0 may also be configured as a
reset source. A block diagram of the Comparator is shown in Figure 1.9.
1.7.
The C8051F350/1/2/3 Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud
rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hard-
ware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
26
Port I/O
Pins
Programmable Comparator
Serial Ports
Figure 1.9. Comparator0 Block Diagram
+
-
GND
VDD
Decision
Reset
Tree
Rev. 1.1
(SYNCHRONIZER)
D
SET
CLR
Q
Q
D
SET
CLR
Interrupt
Q
Q
Logic
(asynchronous output)
(synchronous output)
CP0A
CP0