C8051F367-GM Silicon Laboratories Inc, C8051F367-GM Datasheet - Page 119

• Manufacturer Part Number: C8051F367-GM
• Description: IC 8051 MCU 32K FLASH 28-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F36xr

Specifications of C8051F367-GM

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 28-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F360DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 21-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 28QFN EP
• Device Core: 8051
• Family Name: C8051F36x
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1649

11.3. Operating in Multiply and Accumulate Mode
MAC0 operates in Multiply and Accumulate (MAC) mode when the MAC0MS bit (MAC0CF.0) is cleared to
‘0’. When operating in MAC mode, MAC0 performs a 16-by-16 bit multiply on the contents of the MAC0A
and MAC0B registers, and adds the result to the contents of the 40-bit MAC0 accumulator. Figure 11.4
shows the MAC0 pipeline. There are three stages in the pipeline, each of which takes exactly one SYSCLK
cycle to complete. The MAC operation is initiated with a write to the MAC0BL register. After the MAC0BL
register is written, MAC0A and MAC0B are multiplied on the first SYSCLK cycle. During the second stage
of the MAC0 pipeline, the results of the multiplication are added to the current accumulator contents, and
the result of the addition is stored in the MAC0 accumulator. The status flags in the MAC0STA register are
set after the end of the second pipeline stage. During the second stage of the pipeline, the next multiplica-
tion can be initiated by writing to the MAC0BL register, if it is desired. The rounded (and optionally, satu-
rated) result is available in the MAC0RNDH and MAC0RNDL registers at the end of the third pipeline
stage. If the MAC0CA bit (MAC0CF.3) is set to ‘1’ when the MAC operation is initiated, the accumulator
and all MAC0STA flags will be cleared during the next cycle of the controller’s clock (SYSCLK). The
MAC0CA bit will clear itself to ‘0’ when the clear operation is complete.
11.4. Operating in Multiply Only Mode
MAC0 operates in Multiply Only mode when the MAC0MS bit (MAC0CF.0) is set to ‘1’. Multiply Only mode
is identical to Multiply and Accumulate mode, except that the multiplication result is added with a value of
zero before being stored in the MAC0 accumulator (i.e. it overwrites the current accumulator contents).
The result of the multiplication is available in the MAC0 accumulator registers at the end of the second
MAC0 pipeline stage (two SYSCLKs after writing to MAC0BL). As in MAC mode, the rounded result is
available in the MAC0 Rounding Registers after the third pipeline stage. Note that in Multiply Only mode,
the MAC0HO flag is not affected.
11.5. Accumulator Shift Operations
MAC0 contains a 1-bit arithmetic shift function which can be used to shift the contents of the 40-bit accu-
mulator left or right by one bit. The accumulator shift is initiated by writing a ‘1’ to the MAC0SC bit
(MAC0CF.5), and takes one SYSCLK cycle (the rounded result is available in the MAC0 Rounding Regis-
ters after a second SYSCLK cycle, and MAC0SC is cleared to ‘0’). The direction of the arithmetic shift is
controlled by the MAC0SD bit (MAC0CF.4). When this bit is cleared to ‘0’, the MAC0 accumulator will shift
left. When the MAC0SD bit is set to ‘1’, the MAC0 accumulator will shift right. Right-shift operations are
sign-extended with the current value of bit 39. Note that the status flags in the MAC0STA register are not
affected by shift operations.
MAC0BL
MAC0 Operation
Write
Begins
Multiply
Figure 11.4. MAC0 Pipeline
Operation May
Next MAC0
Be Initiated
MAC0BL
Results Available
Write
Here
Add
Accumulator
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
Multiply
Round
Rounded Results
Add
Available
Round
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