C8051F367-GM Silicon Laboratories Inc, C8051F367-GM Datasheet - Page 135

• Manufacturer Part Number: C8051F367-GM
• Description: IC 8051 MCU 32K FLASH 28-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F36xr

Specifications of C8051F367-GM

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 28-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F360DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 21-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 28QFN EP
• Device Core: 8051
• Family Name: C8051F36x
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1649

C8051F360/1/2/3/4/5/6/7/8/9
13. Flash Memory
All devices include either 32 kB (C8051F360/1/2/3/4/5/6/7) or 16 kB (C8051F368/9) of on-chip, reprogram-
mable Flash memory for program code or non-volatile data storage. The Flash memory can be pro-
grammed in-system through the C2 interface, or by software using the MOVX write instructions. Once
cleared to logic ‘0’, a Flash bit must be erased to set it back to logic ‘1’. Bytes should be erased (set to
0xFF) before being reprogrammed. Flash write and erase operations are automatically timed by hardware
for proper execution. During a Flash erase or write, the FLBUSY bit in the FLSTAT register is set to ‘1’
(see SFR Definition 14.5). During this time, instructions that are located in the prefetch buffer or the branch
target cache can be executed, but the processor will stall until the erase or write is completed if instruction
data must be fetched from Flash memory. Interrupts that have been pre-loaded into the branch target
cache can also be serviced at this time, if the current code is also executing from the prefetch engine or
cache memory. Any interrupts that are not pre-loaded into cache, or that occur while the core is halted, will
be held in a pending state during the Flash write/erase operation, and serviced in priority order once the
Flash operation has completed. Refer to Table 13.2 for the electrical characteristics of the Flash memory.
13.1. Programming the Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initial-
ized device. For details on the C2 commands to program Flash memory, see Section “24. C2 Interface” on
page 284. For detailed guidelines on writing or erasing Flash from firmware, please see Section
“13.3. Flash Write and Erase Guidelines” on page 140.
The Flash memory can be programmed from software using the MOVX write instruction with the address
and data byte to be programmed provided as normal operands. Before writing to Flash memory using
MOVX, Flash write operations must be enabled by setting the PSWE Program Store Write Enable bit
(PSCTL.0) to logic ‘1’. This directs the MOVX writes to Flash memory instead of to XRAM, which is the
default target. The PSWE bit remains set until cleared by software. To avoid errant Flash writes, it is rec-
ommended that interrupts be disabled while the PSWE bit is logic ‘1’.
Flash memory is read using the MOVC instruction. MOVX reads are always directed to XRAM, regardless
of the state of PSWE.
Note: To ensure the integrity of the Flash contents, the on-chip V
Monitor must be enabled in any
DD
system that includes code that writes and/or erases Flash memory from software. Furthermore,
there should be no delay between enabling the V
Monitor and enabling the V
Monitor as a
DD
DD
reset source. Any attempt to write or erase Flash memory while the V
Monitor disabled will
DD
cause a Flash Error device reset.
A write to Flash memory can clear bits but cannot set them; only an erase operation can set bits in Flash.
A byte location to be programmed must be erased before a new value can be written.
Write/Erase timing is automatically controlled by hardware. Note that on the 32 k Flash devices, 1024
bytes beginning at location 0x7C00 are reserved. Flash writes and erases targeting the reserved area
should be avoided.
13.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and
Rev. 1.0
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