MC908AP8ACBE Freescale Semiconductor, MC908AP8ACBE Datasheet - Page 111

• Manufacturer Part Number: MC908AP8ACBE
• Description: IC MCU 8K FLASH 8MHZ 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP8ACBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 30
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Controller Family/series: HC08
• No. Of I/o's: 30
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08AP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908AP64E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period.
7.7 SIM Registers
The SIM has three memory-mapped registers:
Freescale Semiconductor
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•
•
INT/BREAK
SIM Break Status Register
SIM Reset Status Register
SIM Break Flag Control Register
ICLK
IAB
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
CPUSTOP
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
R/W
IDB
IAB
instruction.
Figure 7-19. Stop Mode Recovery from Interrupt
STOP ADDR
STOP +1
Figure 7-18. Stop Mode Entry Timing
MC68HC908AP A-Family Data Sheet, Rev. 3
PREVIOUS DATA
(SBSR) — $FE00
(SRSR) — $FE01
(SBFCR) — $FE03
STOP ADDR + 1
STOP + 2
STOP RECOVERY PERIOD
NOTE
NEXT OPCODE
Figure 7-18
STOP + 2
SAME
shows stop mode entry timing.
SP
SAME
SP – 1
SAME
SAME
SP – 2
SIM Registers
SP – 3
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