MC9S08LL36CLK Freescale Semiconductor, MC9S08LL36CLK Datasheet
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MC9S08LL64 MC9S08LL36 Reference Manual HCS08 Microcontrollers MC9S08LL64RM Rev. 6 1/2010 freescale.com ...
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MC9S08LL64 Series 8-Bit HCS08 Central Processor Unit (CPU) • MHz CPU at 3 2.1 V across temperature range of –40 ° °C • MHz at 2 1.8 V ...
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... Contains descriptive feature set, block diagram, and electrical characteristics for the device. Find the most current versions of all documents at: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2009-2010. All rights reserved. Covers MC9S08LL64 MC9S08LL36 MC9S08LL64RM Rev ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2009-2010. All rights reserved. MC9S08LL64 MCU Series Reference Manual, Rev Description of Changes Original LL64 book prior to product redefinition (includes 16-Bit ADC). Initial Draft after the Product redefinition (includes 12-Bit ADC). Note: Documentation now consists of a Reference Manual (this document) and a Data Sheet ...
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... Serial Peripheral Interface (S08SPIV4) ................................ 291 Chapter 16 Time of Day Module (S08TODV1) ......................................... 309 Chapter 17 Timer Pulse-Width Modulator (S08TPMV3) ......................... 327 Chapter 18 Voltage Reference Module (S08VREFV1) ............................ 349 Chapter 19 Development Support ........................................................... 359 Chapter 20 Debug Module (S08DBGV3) (64K)........................................ 371 MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor List of Chapters Title Page 7 ...
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... Low-Power Wait Mode (LPWait) ......................................................................................44 3.5.1.1 Interrupts in Low-Power Wait Mode ..............................................................44 3.5.1.2 Resets in Low-Power Wait Mode ...................................................................44 3.6 Stop Modes...................................................................................................................................... 44 3.6.1 Stop2 Mode........................................................................................................................45 3.6.2 Stop3 Mode........................................................................................................................46 MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Contents Title Chapter 1 Device Overview Chapter 2 Pins and Connections Chapter 3 Modes of Operation Page ...
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... Flash Options Register (FOPT and NVOPT).....................................................................78 4.9.3 Flash Configuration Register (FCNFG) ............................................................................79 4.9.4 Flash Protection Register (FPROT and NVPROT) ...........................................................79 4.9.5 Flash Status Register (FSTAT)...........................................................................................80 4.9.6 Flash Command Register (FCMD)....................................................................................81 MC9S08LL64 MCU Series Reference Manual, Rev Title Chapter 4 Memory Page Freescale Semiconductor ...
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... Port Slew Rate Enable .....................................................................................................103 6.3.3 Port Drive Strength Select ...............................................................................................103 6.4 Open Drain Operation ................................................................................................................... 103 6.5 Pin Behavior in Stop Modes.......................................................................................................... 103 6.6 Parallel I/O and Pin Control Registers .......................................................................................... 104 MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Title Chapter 5 Chapter 6 Parallel Input/Output Control Page 11 ...
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... Modes of Operation .........................................................................................................121 7.2.1.1 KBI in Wait Mode .........................................................................................121 7.2.1.2 KBI in Stop Modes .......................................................................................121 7.2.1.3 KBI in Active Background Mode .................................................................121 7.2.2 Block Diagram .................................................................................................................121 7.3 External Signal Description .......................................................................................................... 122 MC9S08LL64 MCU Series Reference Manual, Rev Title Chapter 7 Keyboard Interrupt (S08KBIV2) Page Freescale Semiconductor ...
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... Special Operations......................................................................................................................... 133 8.4.1 Reset Sequence ................................................................................................................133 8.4.2 Interrupt Sequence ...........................................................................................................133 8.4.3 Wait Mode Operation.......................................................................................................134 8.4.4 Stop Mode Operation.......................................................................................................134 8.4.5 BGND Instruction............................................................................................................135 8.5 HCS08 Instruction Set Summary .................................................................................................. 137 MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Title Chapter 8 Page 13 ...
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... ICS Control Register 1 (ICSC1) ......................................................................................160 10.3.2 ICS Control Register 2 (ICSC2) ......................................................................................162 10.3.3 ICS Trim Register (ICSTRM)..........................................................................................162 10.3.4 ICS Status and Control (ICSSC)......................................................................................163 10.4 Functional Description .................................................................................................................. 165 10.4.1 Operational Modes...........................................................................................................165 MC9S08LL64 MCU Series Reference Manual, Rev Title Chapter 9 Chapter 10 Page Freescale Semiconductor ...
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... Analog Channel Inputs (ADx) .........................................................................................177 11.4 Register Definition ........................................................................................................................ 177 11.4.1 Status and Control Register 1 (ADCSC1) .......................................................................177 11.4.2 Configuration Register 1(ADCCFG1).............................................................................179 11.4.3 Configuration Register 2 (ADCCFG2)............................................................................180 MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Title Chapter 11 ) .....................................................................................................177 DDA ) ....................................................................................................177 SSA ) ...
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... Sampling Error ..............................................................................................199 11.7.2.2 Pin Leakage Error .........................................................................................199 11.7.2.3 Noise-Induced Errors ....................................................................................199 11.7.2.4 Code Width and Quantization Error .............................................................200 11.7.2.5 Linearity Errors .............................................................................................200 11.7.2.6 Code Jitter, Non-Monotonicity, and Missing Codes .....................................201 MC9S08LL64 MCU Series Reference Manual, Rev Title Page Freescale Semiconductor ...
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... General Call Address .......................................................................................................217 12.5 Resets ............................................................................................................................................ 217 12.6 Interrupts ....................................................................................................................................... 217 12.6.1 Byte Transfer Interrupt.....................................................................................................217 12.6.2 Address Detect Interrupt ..................................................................................................218 12.6.3 Arbitration Lost Interrupt.................................................................................................218 12.7 Initialization/Application Information .......................................................................................... 219 MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Title Chapter 12 Page 17 ...
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... LCD Charge Pump and Voltage Divider .......................................................252 13.4.4.2 LCD Power Supply and Voltage Buffer Configuration ................................253 13.4.5 Resets ...............................................................................................................................257 13.4.6 Interrupts ..........................................................................................................................258 13.5 Initialization Section ..................................................................................................................... 258 13.5.1 Initialization Sequence.....................................................................................................258 MC9S08LL64 MCU Series Reference Manual, Rev Title Chapter 13 ...........................................................................................................226 Page Freescale Semiconductor ...
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... Interrupts and Status Flags...............................................................................................287 14.3.5 Additional SCI Functions ................................................................................................288 14.3.5.1 8- and 9-Bit Data Modes ...............................................................................288 14.3.5.2 Stop Mode Operation ....................................................................................289 14.3.5.3 Loop Mode ....................................................................................................289 14.3.5.4 Single-Wire Operation ..................................................................................289 MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Title Chapter 14 Page 19 ...
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... Introduction ................................................................................................................................... 309 16.1.1 ADC Hardware Trigger ...................................................................................................309 16.1.2 TOD Clock Sources .........................................................................................................309 16.1.3 TOD Modes of Operation ................................................................................................309 16.1.4 TOD Status after Stop2 Wakeup ......................................................................................309 16.1.5 TOD Clock Gating...........................................................................................................309 MC9S08LL64 MCU Series Reference Manual, Rev Title Chapter 15 Chapter 16 Page Freescale Semiconductor ...
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... TPM External Clock ........................................................................................................327 17.1.3 TPM Clock Gating...........................................................................................................327 17.1.4 Features ............................................................................................................................329 17.1.5 Modes of Operation .........................................................................................................329 17.1.6 Block Diagram .................................................................................................................330 17.2 Signal Description ......................................................................................................................... 332 17.2.1 Detailed Signal Descriptions ...........................................................................................332 MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Title Chapter 17 Page 21 ...
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... VREF Clock Gating.........................................................................................................352 18.1.5 VREF Enable ...................................................................................................................352 18.1.6 VREF Output ...................................................................................................................352 18.1.7 Overview..........................................................................................................................353 18.1.8 Features ............................................................................................................................353 18.1.9 Modes of Operation .........................................................................................................354 18.1.10External Signal Description .............................................................................................354 18.2 Memory Map and Register Definition .......................................................................................... 354 MC9S08LL64 MCU Series Reference Manual, Rev Title Chapter 18 Page Freescale Semiconductor ...
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... Register Bit Summary......................................................................................................374 20.3.3 Register Descriptions .......................................................................................................375 20.3.3.1 Debug Comparator A High Register (DBGCAH) ........................................375 20.3.3.2 Debug Comparator A Low Register (DBGCAL) .........................................375 20.3.3.3 Debug Comparator B High Register (DBGCBH) ........................................376 MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Title Chapter 19 Development Support Chapter 20 Page ...
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... Storing Data in FIFO ....................................................................................393 20.4.5.2 Storing with Begin-Trigger ...........................................................................393 20.4.5.3 Storing with End-Trigger ..............................................................................393 20.4.5.4 Reading Data from FIFO ..............................................................................393 20.4.6 Interrupt Priority ..............................................................................................................394 20.5 Resets ............................................................................................................................................ 394 20.6 Interrupts ....................................................................................................................................... 395 20.7 Electrical Specifications................................................................................................................ 395 MC9S08LL64 MCU Series Reference Manual, Rev Title Page Freescale Semiconductor ...
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... RAM ACMP ADC IIC IRQ KBI SCI1 SCI2 SPI TPM1 TPM2 TOD LCD VREFO1 VREFO2 MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor MC9S08LL64 80-pin 64-pin LQFP LQFP 64 KB (32,768 and 32,768 Arrays) 4000 yes 10-ch 8-ch yes yes 8 yes yes ...
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... The 39 I/O pins include two output-only pins and 18 LCD GPIO. 1.2 MCU Block Diagram The block diagram in Figure 1-1 MC9S08LL64 MCU Series Reference Manual, Rev MC9S08LL64 80-pin 64-pin LQFP LQFP 39 37 shows the structure of the MC9S08LL64 series MCU. MC9S08LL36 80-pin 64-pin LQFP LQFP 39 37 Freescale Semiconductor ...
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... V LL3 LIQUID CRYSTAL V DISPLAY CAP1 (LCD) V CAP2 LCD[43:0] Figure 1-1. MC9S08LL64 Series Block Diagram MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor ON-CHIP ICE DEBUG MODULE (DBG) TIME OF DAY MODULE (TOD) KBI[7:0] 8-BIT KEYBOARD INTERRUPT (KBI) BKGD/MS SS SPSCK SERIAL PERIPHERAL MISO ...
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... Serial Peripheral Interface Timer Pulse-Width Modulator Liquid Crystal Display Debug Module Voltage Reference MC9S08LL64 MCU Series Reference Manual, Rev Table 1-2. Module Versions Module (ACMPVLP) (ADC12) (CPU) (KBI) (ICS) (IIC) (XOSCVLP) (TOD) (SCI) (SPI) (TPM) (LCD) (DBG) (VREF) Version Freescale Semiconductor ...
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... See “EXTCLK — External Clock MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor (S08ICSV3),” for details on configuring the ICSOUT (S08ICSV3)” explains the ICSIRCLK in more detail. See (S08TODV1),” for more information regarding the use of (S08TODV1),” ...
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... MC9S08LL64 MCU Series Reference Manual, Rev TCLK TPM1 TPM2 TOD COP FFCLK* SYNC* TODCLK LCD BDC DBG IIC ADC has minimum and maximum frequency requirements. Chapter 16, “Time of Day SCI2 SCI1 SPI ADC12 FLASH Flash has frequency requirements for program and erase operations. Freescale Semiconductor ...
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... PTD4/LCD4 6 PTD3/LCD3 7 PTD2/LCD2 8 PTD1/LCD1 9 PTD0/LCD0 10 V CAP1 11 V CAP2 12 V LL1 13 V LL2 14 V LL3 15 V LCD 16 MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor LCD38 48 LCD39 47 LCD40 46 LCD41 45 44 PTA5/KBIP5/ADP9/LCD42 43 PTA4/KBIP4/ADP8/LCD43 42 PTA3/KBIP3/SCL/MOSI/ADP7 64-Pin LQFP 41 PTA2/KBIP2/SDA/MISO/ADP6 40 PTA1/KBIP1/SPSCK/ADP5 39 PTA0/KBIP0/SS/ADP4 38 PTC7/IRQ/TCLK 37 PTC6/ACMPO/BKGD/MS 36 PTC5/TPM2CH1 35 ...
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... LL1 V 18 LL2 V 19 LL3 V 20 LCD MC9S08LL64 MCU Series Reference Manual, Rev 80-Pin 51 LQFP Figure 2-2. 80-Pin LQFP LCD34 LCD35 LCD36 LCD37 LCD38 LCD39 LCD40 LCD41 PTA5/KBIP5/ADP9/LCD42 PTA4/KBIP4/ADP8/LCD43 PTA3/KBIP3/SCL/MOSI/ADP7 PTA2/KBIP2/SDA/MISO/ADP6 PTA1/KBIP1/SPSCK/ADP5 PTA0/KBIP0/SS/ADP4 PTC7/IRQ/TCLK PTC6/ACMPO/BKGD/MS PTC5/TPM2CH1 PTC4/TPM2CH0 PTC3/TPM1CH1 PTC2/TPM1CH0 Freescale Semiconductor ...
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... Recommended System Connections Figure 2-3 shows pin connections that are common to MC9S08LL64 series application systems. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Chapter 2 Pins and Connections 33 ...
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... PTC2/TPM1CH0 PTC3/TPM1CH1 PTC4/TPM2CH0 C PTC5/TPM2CH1 PTC6/ACMPO/BKGD/MS PTC7/IRQ/TCLK PTD0/LCD0 PTD1/LCD1 PTD2/LCD2 PTD3/LCD3 D PTD4/LCD4 PTD5/LCD5 PTD6/LCD6 PTD7LCD7 PTE0/LCD13 PTE1/LCD14 PTE2/LCD15 PTE3/LCD16 E PTE4/LCD17 PTE5/LCD18 PTE6/LCD19 PTE7LCD20 LCD[43:0] LCD LCD Glass ADP0 ADC ADP12 V OPTIONAL LCD SUPPLY VOLTAGE LCD VREFO ADC x 0.1 μF (NOTE 8) Freescale Semiconductor ...
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... PCB capacitance for each oscillator pin (EXTAL and XTAL). When using the oscillator in low-range and low-gain mode, the external components R are not required. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Chapter 2 Pins and Connections Chapter 6 , “Parallel Input/Output (S08ICSV3)”. ...
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... BKGD/MS pin that could interfere with background serial communications. MC9S08LL64 MCU Series Reference Manual, Rev NOTE DD . The internal gates connected to this pin are pulled to Figure 2-3 for an example. and must not be driven level, an external DD Section 5.8.3, “System Background Freescale Semiconductor ...
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... When a port pin is configured as a general-purpose input or when a peripheral uses the port pin as an input, software can enable a pullup device. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor , and V pins are dedicated to providing power to the LCD CAP1 CAP2 Chapter 13, “ ...
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... PTA7 22 MC9S08LL64 MCU Series Reference Manual, Rev However, the internal voltage on the PTB2 DD Control.” NOTE <-- Lowest Priority --> Highest Alt 1 Alt 2 LCD13 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 KBIP6 ADP10 KBIP7 ADP11 Alt3 Alt4 ACMP+ ACMP– Freescale Semiconductor ...
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... PTA5 53 45 LCD41 54 46 LCD40 LCD39 LCD38 57 LCD37 LCD36 58 59 LCD35 MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor <-- Lowest Priority --> Highest Alt 1 Alt 2 EXTAL XTAL RESET MISO SDA MOSI SCL RxD2 SPSCK TxD2 SS RxD1 TxD1 TPM1CH0 TPM1CH1 TPM2CH0 TPM2CH1 ...
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... LCD23 72 57 LCD22 73 58 LCD21 74 59 PTE7 75 60 PTE6 76 61 PTE5 77 62 PTE4 78 63 PTE3 79 64 PTE2 80 1 PTE1 MC9S08LL64 MCU Series Reference Manual, Rev <-- Lowest Priority --> Highest Alt 1 Alt 2 LCD20 LCD19 LCD18 LCD17 LCD16 LCD15 LCD14 Alt3 Alt4 Freescale Semiconductor ...
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... Before entering this mode, the following conditions must be met: • FBELP is the selected clock mode for the ICS. • The HGO bit in the ICSC2 register is clear. • The bus frequency is less than 125 kHz. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor 41 ...
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... When the BKGD/MS pin is low immediately after issuing a background debug force reset (see Section 5.8.3, “System Background Debug Force Reset Register • When a BACKGROUND command is received through the BKGD/MS pin • When a BGND instruction is executed MC9S08LL64 MCU Series Reference Manual, Rev (SBDFR)) Freescale Semiconductor ...
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... MCU is operated in run mode for the first time. When the MC9S08LL64 Series is shipped from the Freescale Semiconductor factory, the flash program memory is erased by default unless specifically noted result, no program can be executed in run mode until the flash memory is initially programmed ...
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... SOPT1 BDCSCR 1 Bit name STOPE ENBDM 0 x MC9S08LL64 MCU Series Reference Manual, Rev Table 3-1. Stop Mode Selection SPMSC1 SPMSC2 LVDE LVDSE PPDC x x Stop modes disabled; illegal opcode reset if STOP instruction executed Chapter 10, “Internal Clock Source Stop Mode Freescale Semiconductor ...
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... In addition to the above, upon waking from stop2, the PPDF bit in SPMSC2 is set. This flag is used to direct user code stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until written to PPDACK in SPMSC2. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Table 3-1. Stop Mode Selection (continued) SPMSC1 SPMSC2 ...
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... The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) the voltage MC9S08LL64 MCU Series Reference Manual, Rev Support.” If ENBDM is set when the CPU Freescale Semiconductor Table 3-1. The ...
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... WAIT instruction executed.) STOP3 - (Assumes STOPE 0 bit is set and STOP 0 instruction executed.) Note 0 that STOP3 is used in place of STOP2 if the BDM or LVD is enabled. 1 MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Table 3-2. Power Mode Selections SPMSC1 SPMSC2 PMC PMC 1 LVDE LVDSE LPR PPDC x x ...
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... CPU & Periph CLKs Voltage BDM Clock Regulator OSCOUT off 2,3 optionally on powerdown Mode Regulator State RUN Full on WAIT Full on LPRUN Standby LPWAIT Standby STOP3 Standby STOP2 Partial powerdown Table 3-1. Figure 3-1. Figure 3-1. Trigger Table 3-1, switch Freescale Semiconductor partial ...
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... Table 3-4. Stop and Low Power Mode Behavior Peripheral CPU RAM FLASH Port I/O Registers ADC12 ACMP MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Figure To Pre-configure settings shown in STOP2 STOP instruction assert zero on PTB2/RESET RUN assert a TOD interrupt, or reload environment ...
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... Section 3.6.4, “LVD Enabled in Stop Mode LPWait LPRun 4 Off Off Optionally On Optionally Optionally On Optionally On Optionally On Optionally On Optionally On Optionally On 8 Off Off 9 Optionally On Optionally On 10 Optionally On Optionally On Optionally On Optionally On Optionally On Optionally On Optionally On Optionally On Optionally On Optionally On Standby Standby Optionally On Optionally On Peripheral Control On Mode”. Freescale Semiconductor ...
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... I/O and control/status registers. The registers are divided into four groups: • Direct-page registers (0x0000 through 0x005F) • LCD data registers (0x1000 through 0x103B) • High-page registers (0x1800 through 0x18A0) • Nonvolatile registers (0xFFB0 through 0xFFBF) MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor 51 ...
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... BYTES 0xBFFF 0xC000 PPAGE=3 FLASH 0xFFFF Figure 4-1. MC9S08LL36 Memory Map PPAGE=7 PPAGE=6 PPAGE=5 RESERVED PPAGE=4 16384 BYTES RESERVED 16384 BYTES 16384 BYTES RESERVED PPAGE=1 PPAGE=2 PPAGE=3 FLASH FLASH 8,192 BYTES FLASH 12,288 BYTES 16,384 BYTES RESERVED RESERVED Freescale Semiconductor ...
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... Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale Semiconductor provided equate file for the MC9S08LL64 series. Address (High/Low) 0xFFC0:FFC1 0xFFD0:FFD1 ...
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... TPM2 Channel 0 TPM1 Overflow TPM1 Channel 1 TPM1 Channel 0 Low Voltage Detect or Low Voltage Warning IRQ SWI Reset Vector Name Vtod Vacmp Vadc Vkeyboard Viic Vsci1tx Vsci1rx Vsci1err Vspi Vlcd Vtpm2ovf Vtpm2ch1 Vtpm2ch0 Vtpm1ovf Vtpm1ch1 Vtpm1ch0 Vlvd Virq Vswi Vreset Freescale Semiconductor ...
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... Shaded cells with dashes indicate unused or reserved bit locations that could read 0s. When writing to these bits, write a 0 unless otherwise specified. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor can use the more efficient direct addressing mode, which requires 4-5, the whole address in column one is shown in bold. In ...
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... ACOPE ACMOD SBR11 SBR10 SBR9 SBR3 SBR2 SBR1 WAKE ILT RWU RWUID BRK13 LBKDE ORIE NEIE FEIE Freescale Semiconductor Bit 0 PTAD0 PTADD0 PTBD0 PTBDD0 PTCD0 PTCDD0 PTDD0 PTDDD0 PTED0 PTEDD0 — — KBIMOD KBIPE0 KBEDG0 IRQMOD — — — DUTY0 LCDSTP ...
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... TPM1C1SC CH1F 0x0049 TPM1C1VH Bit 15 0x004A TPM1C1VL Bit 7 0x004B- — Reserved 0x004F — 0x0050 TPM2SC TOF 0x0051 TPM2CNTH Bit 15 0x0052 TPM2CNTL Bit 7 MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor SPE SPTIE MSTR 0 0 MODFEN SPPR2 SPPR1 SPPR0 0 SPTEF MODF — ...
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... BPDLCD0 BPCLCD0 BPBLCD0 BPDLCD1 BPCLCD1 BPBLCD1 BPDLCD2 BPCLCD2 BPBLCD2 BPDLCD3 BPCLCD3 BPBLCD3 BPDLCD4 BPCLCD4 BPBLCD4 Freescale Semiconductor Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — Bit 0 PEN0 PEN8 PEN16 PEN24 PEN32 PEN40 — — ...
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... LCDWF41 BPHLCD41 BPGLCD41 BPFLCD41 BPELCD41 BPDLCD41 BPCLCD41 BPBLCD41 BPALCD41 0x103A LCDWF42 BPHLCD42 BPGLCD42 BPFLCD42 BPELCD42 BPDLCD42 BPCLCD42 BPBLCD42 BPALCD42 0x103B LCDWF43 BPHLCD43 BPGLCD43 BPFLCD43 BPELCD43 BPDLCD43 BPCLCD43 BPBLCD43 BPALCD43 Freescale Semiconductor Table 4-3. LCD Registers (Sheet BPGLCD5 BPFLCD5 BPELCD5 BPGLCD6 ...
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... ACMP TOD LCD bit- bit- bit- LOOP1 TRG ARMF CNT DIV 0 0 SEC — — — FPDIS Freescale Semiconductor Bit 0 0 ACIC — — ID8 ID0 — 0 — — SCI1 SPI Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 0 — 0 ...
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... SCI2C2 TIE 0x185C SCI2S1 TDRE 0x185D SCI2S2 LBKDIF 0x185E SCI2C3 R8 0x185F SCI2D Bit 7 0x1860 IICA AD7 MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor FCCF FPVIOL FACCERR FCMD — — — — — — TODCLKS TODR TODCLKEN SECF MTCHF QSECIE ...
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... SRW IICIF 0 AD10 AD9 — — — CV[11:8] — — — — — — — 0 — ADCO — — — — — ADPC3 ADPC2 ADPC1 ADPC0 ADPC11 ADPC10 ADPC9 ADPC8 Freescale Semiconductor Bit 0 0 RXAK AD8 — — — — ...
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... Memory Management Unit extends the HCS08 memory space — for program and data space (Maximum) • Extended program space using paging scheme — PPAGE register used for page selection — fixed 16 KB memory window MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor VREF1 TRIM VREF2 TRIM 0 ...
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... The contents of LAP1:LAP0 will auto-increment when accessing data using the LBP and LWP registers. The contents of LAP1:LAP0 can be increased by writing an 8-bit value to LAPAB. MC9S08LL64 MCU Series Reference Manual, Rev Figure 4-3. Program Page Register (PPAGE) Description XA15 XA14 Freescale Semiconductor 0 0 ...
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... When LBP is accessed the contents of LAP1:LAP0 make up the extended address of the flash memory location to be addressed. When accessing data using LBP, the contents of LAP1:LAP0 will increment after the read or write is complete. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor LA13 LA12 LA11 ...
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... Linear Address Pointer Add Byte Register (LAPAB) The user can increase or decrease the contents of LAP1:LAP0 by writing a 2s compliment value to LAPAB. The value written will be added to the current contents of LAP1:LAP0. MC9S08LL64 MCU Series Reference Manual, Rev Description Figure 4-7. Linear Byte Register (LB) Description Freescale Semiconductor ...
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... CALL is similar to a JSR instruction, but the subroutine that is called can be located anywhere in the normal 64 KB address space or on any page of program memory. During the execution of a CALL instruction, the CPU: • Stacks the return address. • Pushes the current PPAGE value onto the stack. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor ...
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... LAP1:LAP0. 4.5.3.1.4 PPAGE and Linear Address Pointer to Extended Address See Figure 4-3, on how the program PPAGE memory pages and the linear address pointer are mapped to extended address space. MC9S08LL64 MCU Series Reference Manual, Rev Freescale Semiconductor ...
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... MC9S08LL64 series usually best to reinitialize the stack pointer to the top of the RAM so the direct-page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale Semiconductor-provided equate file). LDHX #RamLast+1 ...
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... FCLK FCLK FCLK Table 4-12. Program and Erase Times Cycles of FCLK 9 4 4000 20,000 ) between 150 kHz and 200 kHz FCLK . The times are shown as a number = 5 μs. Program and erase times Time if FCLK = 200 kHz 45 μs 20 μ 100 ms Freescale Semiconductor ...
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... Figure 4-9 programming. The FCDIV register must be initialized before using any flash commands. This must be done only once following a reset. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor NOTE is a flowchart for executing all of the commands except for burst Chapter 4 Memory ...
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... FACCERR OR FPVIOL? 1 CLEAR ERRORS WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF (2) Wait at least four bus cycles before checking FCBEF or FCCF. TO LAUNCH COMMAND (2) AND CLEAR FCBEF YES FPVIOL OR FACCERR (3) FCCF? 1 DONE Required only once ERROR EXIT Freescale Semiconductor ...
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... FACCERR error. Such as executing a STOP instruction or writing to the flash. Reads of the flash during program or erase are ignored and invalid data is returned. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor (1) WRITE TO FCDIV START FACCERR OR FPVIOL? 1 CLEAR ERRORS FCBEF? 1 WRITE TO Flash ...
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... For example, to protect the last 1536 bytes of memory (addresses 0xFA00 through 0xFFFF), the FPS bits must be set to 1111 100, which results in the value 0xF9FF as the last address of unprotected MC9S08LL64 MCU Series Reference Manual, Rev NVPROT)”). Figure 4-11. The FPS bits are used as the upper bits of Section 4.9.4, “Flash Freescale Semiconductor ...
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... FOPT register. During reset, the contents of the nonvolatile location NVOPT are copied from flash into the working FOPT register in high-page register space. A user engages security by programming the NVOPT location which can be done at the same time the flash memory is programmed. The 1:0 state MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor 1 A12 A11 ...
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... To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00 = 1:0. 4.9 Flash Registers and Control Bits The flash module has nine 8-bit registers in the high-page register space. Two locations (NVOPT, NVPROT) in the nonvolatile register space in flash memory are copied into corresponding high-page MC9S08LL64 MCU Series Reference Manual, Rev Freescale Semiconductor ...
Page 77
... Table 4-5 for the absolute address assignments for all flash registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file is normally used to translate these names into the appropriate absolute addresses. 4.9.1 Flash Clock Divider Register (FCDIV) Bit 7 of this register is a read-only flag ...
Page 78
... Figure 4-13. Flash Options Register (FOPT) Description Section 4.8, Section 4.8, Program/Erase Timing Pulse (5 μs Min, 6.7 μs Max) 5.2 μs 5 μs 5 μs 5 μs 5 μs 5 μs 5 μs 6.7 μ SEC01 “Security.” Table “Security.” Freescale Semiconductor 0 SEC00 4-16. When ...
Page 79
... This register is loaded from nonvolatile location NVPROT during reset. 1 Background commands can be used to change the contents of these bits in FPROT. Figure 4-15. Flash Protection Register (FPROT) MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Table 4-16. Security States SEC01:SEC00 Description 0:0 secure ...
Page 80
... FPVIOL is cleared by writing FPVIOL protection violation attempt was made to erase or program a protected location. MC9S08LL64 MCU Series Reference Manual, Rev Description 5 4 FPVIOL FACCERR 0 0 Figure 4-16. Flash Status Register (FSTAT) Description FBLANK Freescale Semiconductor ...
Page 81
... It is not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the security unlocking mechanism. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Description Section 4.7.5, “Access Execution,” for a detailed discussion of flash programming and erase ...
Page 82
... Chapter 4 Memory MC9S08LL64 MCU Series Reference Manual, Rev Freescale Semiconductor ...
Page 83
... Illegal address detect (ILAD)(MC9S08LL36 devices only) • Low-voltage detect (LVD) • Background debug forced reset Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register (SRS). MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Table 5-2) 83 ...
Page 84
... Table 5-1. COP Configuration Options Clock Source COPT 0 ~1 kHz 1 ~1 kHz 0 Bus 1 Bus = 1 ms. See t LPO Section 5.8.4, “System (SOPT2),” for additional COP Overflow Count cycles (32 ms cycles (256 ms cycles 18 2 cycles in the data sheet for the LPO Freescale Semiconductor ...
Page 85
... RTI that is used to return from the ISR. If more than one interrupt is pending when the I bit is cleared, the highest priority source is serviced first (see Table 5-2). MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control NOTE 85 ...
Page 86
... CONDITION CODE REGISTER 4 2 ACCUMULATOR * INDEX REGISTER (LOW BYTE PROGRAM COUNTER HIGH 1 5 PROGRAM COUNTER LOW TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame 0 SP AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT Freescale Semiconductor ...
Page 87
... CCR the CPU will finish the current instruction; stack the PCL, PCH and CCR CPU registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control 87 ...
Page 88
... TPM2 channel 0 TOIE TPM1 overflow CH1IE TPM1 channel 1 CH0IE TPM1 channel 0 LVDIE, LVWIE Low-voltage detect, Low-voltage warning IRQIE IRQ pin — Software interrupt COPE Watchdog timer LVDRE Low-voltage detect RSTPE External pin — Illegal opcode — Illegal address ) or LVDH Freescale Semiconductor ...
Page 89
... User software must disable the peripheral before disabling the clocks to the peripheral. When clocks are re-enabled to a peripheral, the peripheral registers need to be re-initialized by user software. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control ) and one low (V ). The trip voltage is selected ...
Page 90
... IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can IRQPE be used as an interrupt request. 0 IRQ pin function is disabled. 1 IRQ pin function is enabled. MC9S08LL64 MCU Series Reference Manual, Rev Chapter 4 , “Memory,” of this reference manual for the absolute IRQF IRQEDG IRQPE Description IRQIE IRQMOD IRQACK Freescale Semiconductor ...
Page 91
... Any of these reset sources that are active at the time of reset entry will cause the corresponding bit( set; bits corresponding to sources that are not active at the time of reset entry will be cleared. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control Description Sensitivity” ...
Page 92
... W Reset Unimplemented or Reserved 1 BDFR is writable only through serial background debug commands, not from user programs. Figure 5-4. System Background Debug Force Reset Register (SBDFR) MC9S08LL64 MCU Series Reference Manual, Rev Table 5-4. SRS Register Field Descriptions Description Freescale Semiconductor BDFR 0 ...
Page 93
... Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user STOPE program attempts to execute a STOP instruction, an illegal opcode reset is forced. 0 Stop mode disabled. 1 Stop mode enabled. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control Description ...
Page 94
... Chapter 9, “Analog Comparator (S08ACMPVLPV1) (S08TPMV3)” for more details on this feature. 0 ACMP output not connected to TPM2 input channel 0. 1 ACMP output connected to TPM2 input channel 0. MC9S08LL64 MCU Series Reference Manual, Rev Description Description and Chapter 17, “Timer Pulse-Width Modulator SPIPS IICPS ACIC Freescale Semiconductor ...
Page 95
... Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The ID[7:0] MC9S08LL64 is hard coded to the value 0x026. See also ID bits in MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control ID11 — ...
Page 96
... Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the BGBE ADC module on one of its internal channels. 0 Bandgap Buffer is disabled. 1 Bandgap Buffer is enabled. MC9S08LL64 MCU Series Reference Manual, Rev Table 5-12 for the LVDV bit description in SPMSC3 LVDIE LVDRE LVDSE Description LVDE BGBDS BGBE Unaffected by reset Freescale Semiconductor ...
Page 97
... LPR=1. If PPDC and LPR are set in a single write instruction, only PPDC will actually be set. 0 Stop3 low power mode enabled. 1 Stop2 partial power down mode enabled. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control Section 3.3.1, “Low-Power Run Mode (LPWait),” and ...
Page 98
... V Supply Description = V ). LVD LVOL = V ). LVD LVOH = V ). LVW LVWL = V ). LVW LVWH LVW Trip Point V = 2.16 V LVWL V = 2.46 V LVWH V = 2.16 V LVWL V = 2.46 V LVWH Unaffected by reset is already below V . Supply LVW ). LVD ). LVW 1 LVD Trip Point V = 1.82 V LVDL V = 2.16 V LVDH Freescale Semiconductor ...
Page 99
... SCI1 Clock Gate Control — This bit controls the clock gate to the SCI1 module. SCI1 0 Bus clock to the SCI1 module is disabled. 1 Bus clock to the SCI1 module is enabled. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control Gating,” for more information. NOTE 5 ...
Page 100
... SPI Clock Gate Control — This bit controls the clock gate to the SPI module. SPI 0 Bus clock to the SPI module is disabled. 1 Bus clock to the SPI module is enabled. MC9S08LL64 MCU Series Reference Manual, Rev. 6 100 Gating,” for more information. NOTE IRQ KBI ACMP Description TOD LCD SPI Freescale Semiconductor ...
Page 101
... The input buffer for the associated pin is always enabled unless the pin is enabled as an analog function output-only pin. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Connections,” for more information about pin assignments and external Table 2-1 ...
Page 102
... The pullup device is disabled if the pin is controlled by an analog function or any shared peripheral function regardless of the state of the corresponding pullup enable register bit. MC9S08LL64 MCU Series Reference Manual, Rev. 6 102 PTxDDn D Q PTxDn Figure 6-1. Parallel I/O Block Diagram Output Enable Output Data Input Data Synchronizer Freescale Semiconductor ...
Page 103
... If the LCD module is configured to operate in stop modes, the drive mode of the GPIO shared with LCD will be retained upon stop recovery. • In stop3 mode, all I/O is maintained because internal logic circuitry stays powered up. Upon recovery, normal I/O function is available to the user. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Chapter 6 Parallel Input/Output Control 103 ...
Page 104
... MC9S08LL64 MCU Series Reference Manual, Rev. 6 104 is connected to V LL3 PTAD5 PTAD4 PTAD3 0 0 Figure 6-2. Port A Data Register (PTAD) Table 6-1. PTAD Register Field Descriptions Description externally, VSUPPLY = 11 PTAD2 PTAD1 Freescale Semiconductor 0 PTAD0 0 ...
Page 105
... PTA pin. For port A pins that are configured as outputs (except for PTA4 and PTA5), these bits have no effect and the internal pull devices are disabled. 0 Internal pullup/pulldown device disabled for port A bit n. 1 Internal pullup/pulldown device enabled for port A bit n. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor ...
Page 106
... PTA pin. For port A pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port A bit n. 1 High output drive strength selected for port A bit n. MC9S08LL64 MCU Series Reference Manual, Rev. 6 106 PTASE5 PTASE4 PTASE3 Description PTADS5 PTADS4 PTADS3 Description PTASE2 PTASE1 PTASE0 PTADS2 PTADS1 PTADS0 Freescale Semiconductor ...
Page 107
... Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for PTBDD[7:0] PTBD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor 5 4 PTBD5 PTBD4 0 0 Figure 6-7 ...
Page 108
... PTB pin. For port B pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port B bit n. 1 Output slew rate control enabled for port B bit n. MC9S08LL64 MCU Series Reference Manual, Rev. 6 108 PTBPE5 PTBPE4 Description PTBSE5 PTBSE4 Description PTBPE2 PTBPE1 PTBPE0 PTBSE2 PTBSE1 PTBSE0 Freescale Semiconductor ...
Page 109
... High output drive strength selected for port B bit n. 6.6.3 Port C Registers Port C is controlled by the registers listed below. The pin PTC6 is unique. PTC6 is an output only, so the control bits for the input functions have no effect on this pin. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor PTBDS5 PTBDS4 ...
Page 110
... Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn. MC9S08LL64 MCU Series Reference Manual, Rev. 6 110 PTCD5 PTCD4 PTCD3 Figure 6-12. Port C Data Register (PTCD) Description PTCDD5 PTCDD4 PTCDD3 Description PTCD2 PTCD1 PTCD0 PTCDD2 PTCDD1 PTCDD0 Freescale Semiconductor ...
Page 111
... PTC pin. For port C pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port C bit n. 1 Output slew rate control enabled for port C bit n. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor ...
Page 112
... PTC pin. For port C pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port C bit n. 1 High output drive strength selected for port C bit n. MC9S08LL64 MCU Series Reference Manual, Rev. 6 112 PTCDS5 PTCDS4 PTCDS3 Description PTCDS2 PTCDS1 PTCDS0 Freescale Semiconductor ...
Page 113
... Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for PTDDD[7:0] PTDD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor is connected to V LL3 ...
Page 114
... PTD pin. 0 Output slew rate control disabled for port D bit n. 1 Output slew rate control enabled for port D bit n. MC9S08LL64 MCU Series Reference Manual, Rev. 6 114 PTDPE5 PTDPE4 PTDPE3 Description PTDSE5 PTDSE4 PTDSE3 Description PTDPE2 PTDPE1 PTDPE0 PTDSE2 PTDSE1 PTDSE0 Freescale Semiconductor ...
Page 115
... PTD pin. For port D pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port D bit n. 1 High output drive strength selected for port D bit n. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor ...
Page 116
... Output driver enabled for Port E bit n and PTED reads return the contents of PTEDn. MC9S08LL64 MCU Series Reference Manual, Rev. 6 116 is connected to V LL3 PTED5 PTED4 PTED3 Figure 6-22. Port E Data Register (PTED) Description PTEDD5 PTEDD4 PTEDD3 Description externally, VSUPPLY = 11, FCDEN = 2 1 PTED2 PTED1 PTED0 PTEDD2 PTEDD1 PTEDD0 0 0 Freescale Semiconductor ...
Page 117
... Output Slew Rate Enable for Port E Bits — Each of these control bits determines if the output slew rate control PTESE[7:0] is enabled for the associated PTE pin. 0 Output slew rate control disabled for port E bit n. 1 Output slew rate control enabled for port E bit n. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor PTEPE5 PTEPE4 ...
Page 118
... Chapter 6 Parallel Input/Output Control MC9S08LL64 MCU Series Reference Manual, Rev. 6 118 Freescale Semiconductor ...
Page 119
... The bus clock to the KBI can be gated on and off using the KBI bit in SCGC2. This bit is set after any reset, which enables the bus clock to this module. To conserve power, this bit can be cleared to disable the clock to this module when not in use. See MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Section 5.7, “Peripheral Clock Gating,” for details. 119 ...
Page 120
... PTA4/KBIP4/ADP8/LCD43 PTA3/KBIP3/SCL/MOSI/ADP7 PTA2/KBIP2/SDA/MISO/ADP6 PTA1/KBIP1/SPSCK/ADP5 PTA0/KBIP0/SS/ADP4 PTB7/TxD2/SS PTB6/RxD2/SPSCK PTB5/MOSI/SCL PTB4/MISO/SDA ∞ PTB2/RESET PTB1/XTAL PTB0/EXTAL PTC7/IRQ/TCLK ◊ PTC6/ACMPO//BKGD/MS PTC5/TPM2CH1 PTC4/TPM2CH0 PTC3/TPM1CH1 PTC2/TPM1CH0 PTC1/TxD1 PTC0/RxD1 • ADP0 • • ADP12 • PTD[7:0]/LCD[7:0] PTE[7:0]/LCD[13:20] and V for the 64-pin DDA SSA Freescale Semiconductor ...
Page 121
... KBI in Active Background Mode When the microcontroller is in active background mode, the KBI will continue to operate normally. 7.2.2 Block Diagram The block diagram for the keyboard interrupt module is shown MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Chapter 7 Keyboard Interrupt (S08KBIV2) Figure 7-2. 121 ...
Page 122
... Table 7-1. KBI Pin Mapping PTA5 PTA4 PTA3 KBIP75 KBIP4 KBIP3 Memory chapter for the absolute address assignments for KBF BUSCLK KBF SYNCHRONIZER STOP BYPASS KBI STOP INTERRUPT REQUES T KBIE PTA2 PTA1 PTA0 KBIP2 KBIP1 KBIP0 KBIE KBIMOD KBACK Freescale Semiconductor ...
Page 123
... Table 7-3. KBIPE Register Field Descriptions Field 7:0 KBI Interrupt Pin Selects — Each of the KBIPEn bits enable the corresponding KBI interrupt pin. KBIPE[7:0] 0 Pin not enabled as interrupt. 1 Pin enabled as interrupt. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Description KBIPE5 KBIPE4 KBIPE3 ...
Page 124
... A valid edge on an enabled port pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented to the CPU. Clearing of KBF is accomplished by writing KBACK in KBISC. MC9S08LL64 MCU Series Reference Manual, Rev. 6 124 KBEDG5 KBEDG4 KBEDG3 Description KBEDG2 KBEDG1 KBEDG0 Freescale Semiconductor ...
Page 125
... If using internal pullup/pulldown device, configure the associated pull enable bits in KBIPE. 4. Enable the interrupt pins by setting the appropriate KBIPEn bits in KBIPE. 5. Write to KBACK in KBISC to clear any false interrupts. 6. Set KBIE in KBISC to enable interrupts. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Chapter 7 Keyboard Interrupt (S08KBIV2) 125 ...
Page 126
... Chapter 7 Keyboard Interrupt (S08KBIV2) MC9S08LL64 MCU Series Reference Manual, Rev. 6 126 Freescale Semiconductor ...
Page 127
... This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several ...
Page 128
... X. MC9S08LL64 MCU Series Reference Manual, Rev. 6 128 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 8-1. CPU Registers Freescale Semiconductor ...
Page 129
... For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Central Processor Unit (S08CPUV4)Chapter 8 Central Processor Unit (S08CPUV4) 129 ...
Page 130
... No carry out of bit 7 1 Carry out of bit 7 MC9S08LL64 MCU Series Reference Manual, Rev. 6 130 CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 8-2. Condition Code Register Table 8-1. CCR Register Field Descriptions Description Freescale Semiconductor ...
Page 131
... In immediate addressing mode, the operand needed to complete the instruction is included in the object code immediately following the instruction opcode in memory. In the case of a 16-bit immediate operand, MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Central Processor Unit (S08CPUV4)Chapter 8 Central Processor Unit (S08CPUV4) NOTE ...
Page 132
... The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is used only for the CBEQ instruction. MC9S08LL64 MCU Series Reference Manual, Rev. 6 132 Freescale Semiconductor ...
Page 133
... The CPU sequence for an interrupt is: 1. Store the contents of PCL, PCH and CCR on the stack, in that order. 2. Set the I bit in the CCR. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Central Processor Unit (S08CPUV4)Chapter 8 Central Processor Unit (S08CPUV4) Resets, Interrupts, and System Configuration 133 ...
Page 134
... MCU was reset into active background mode), the oscillator is forced to remain active when the MCU enters stop mode. In this case serial BACKGROUND command is issued to the MCU through the background debug interface MC9S08LL64 MCU Series Reference Manual, Rev. 6 134 Freescale Semiconductor ...
Page 135
... PPAGE value and the return address, the queue is refilled, and execution resumes with the next instruction after the corresponding CALL. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Central Processor Unit (S08CPUV4)Chapter 8 Central Processor Unit (S08CPUV4) chapter for more details. 135 ...
Page 136
... However subroutine can be called from other pages, it must be terminated with an RTC. In this case, since RTC unstacks the PPAGE value as well as the return address, all accesses to the subroutine, even those made from the same page, must use CALL instructions. MC9S08LL64 MCU Series Reference Manual, Rev. 6 136 Freescale Semiconductor ...
Page 137
... ASL oprx8,X b7 ASL ,X ASL oprx8,SP (Same as LSL) ASR opr8a Arithmetic Shift Right ASRA ASRX ASR oprx8,X ASR , ASR oprx8,SP Freescale Semiconductor Central Processor Unit (S08CPUV4)Chapter 8 Central Processor Unit (S08CPUV4) Object Code IMM DIR EXT IX2 IX1 IX SP2 9E D9 SP1 9E E9 IMM ...
Page 138
... Freescale Semiconductor Affect on CCR – – – – – – – – – – – – – – – – – – – – – – – – – – – – ...
Page 139
... CLR opr8a Clear A ← $00 CLRA X ← $00 CLRX H ← $00 CLRH M ← $00 CLR oprx8,X M ← $00 CLR ,X M ← $00 CLR oprx8,SP Freescale Semiconductor Central Processor Unit (S08CPUV4)Chapter 8 Central Processor Unit (S08CPUV4) Object Code REL REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) REL ...
Page 140
... rpp prpp prpp – rpp 3 F8 rfp pprpp 4 ff prpp Freescale Semiconductor Affect on CCR – – – – – – – – – – – – – – – – – – – ...
Page 141
... LSL oprx8,X b7 LSL ,X (Same as ASL) LSL oprx8,SP LSR opr8a Logical Shift Right LSRA LSRX 0 LSR oprx8,X LSR ,X b7 LSR oprx8,SP Freescale Semiconductor Central Processor Unit (S08CPUV4)Chapter 8 Central Processor Unit (S08CPUV4) Object Code DIR INH INH IX1 IX SP1 9E 6C DIR EXT IX2 IX1 ...
Page 142
... Freescale Semiconductor Affect on CCR – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ...
Page 143
... STX opr8a STX opr16a STX oprx16,X Store X (Low 8 Bits of Index Register) STX oprx8,X in Memory M ← (X) STX ,X STX oprx16,SP STX oprx8,SP Freescale Semiconductor Central Processor Unit (S08CPUV4)Chapter 8 Central Processor Unit (S08CPUV4) Object Code INH INH INH INH IMM DIR EXT IX2 IX1 ...
Page 144
... Freescale Semiconductor Affect on CCR – – 1 – – – – – – – – – – – – – – – – – – – – – ...
Page 145
... V Overflow bit H Half-carry bit I Interrupt mask N Negative bit Z Zero bit C Carry/borrow bit Freescale Semiconductor Central Processor Unit (S08CPUV4)Chapter 8 Central Processor Unit (S08CPUV4) Object Code INH INH Addressing Modes: DIR Direct addressing mode EXT Extended addressing mode IMM Immediate addressing mode INH ...
Page 146
... IMM 2 DIR 3 EXT 3 IX2 TXA AIX STX STX STX INH 2 IMM 2 DIR 3 EXT 3 IX2 Opcode HCS08 Cycles Hexadecimal SUB Instruction Mnemonic Addressing Mode Number of Bytes 1 IX Freescale Semiconductor SUB SUB 2 IX1 CMP CMP 2 IX1 SBC SBC 2 IX1 CPX CPX 2 IX1 1 IX ...
Page 147
... Indexed, 16-Bit Offset DD DIR to DIR IMD IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E) Freescale Semiconductor Central Processor Unit (S08CPUV4)Chapter 8 Central Processor Unit (S08CPUV4) Table 8-3. Opcode Map (Sheet Read-Modify-Write Control 9E60 6 NEG 3 SP1 ...
Page 148
... Central Processor Unit (S08CPUV4)Chapter 8 Central Processor Unit (S08CPUV4) MC9S08LL64 MCU Series Reference Manual, Rev. 6 148 Freescale Semiconductor ...
Page 149
... To conserve power, the ACMP bit can be cleared to disable the clock to this module when not in use. See MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Chapter 18, “Voltage Reference Module Section 5.7, “Peripheral Clock Gating,” ...
Page 150
... PTA4/KBIP4/ADP8/LCD43 PTA3/KBIP3/SCL/MOSI/ADP7 PTA2/KBIP2/SDA/MISO/ADP6 PTA1/KBIP1/SPSCK/ADP5 PTA0/KBIP0/SS/ADP4 PTB7/TxD2/SS PTB6/RxD2/SPSCK PTB5/MOSI/SCL PTB4/MISO/SDA ∞ PTB2/RESET PTB1/XTAL PTB0/EXTAL PTC7/IRQ/TCLK ◊ PTC6/ACMPO//BKGD/MS PTC5/TPM2CH1 PTC4/TPM2CH0 PTC3/TPM1CH1 PTC2/TPM1CH0 PTC1/TxD1 PTC0/RxD1 • ADP0 • • ADP12 • PTD[7:0]/LCD[7:0] PTE[7:0]/LCD[13:20] and V for the 64-pin DDA SSA Freescale Semiconductor ...
Page 151
... When the microcontroller is in active background mode, the ACMP continues to operate normally. When ACMPO is shared with the BKGD pin and the BKGD pin is enabled, the ACMPO function is not available. 9.1.6 Block Diagram The block diagram for the ACMP module follows. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Analog Comparator (S08ACMPVLPV1) 151 ...
Page 152
... Unimplemented Figure 9-3. ACMP Status and Control Register (ACMPSC) MC9S08LL64 MCU Series Reference Manual, Rev. 6 152 Internal Bus ACBGS Status & Control ACPE Register ACO + Interrupt Control – ACO ACF ACIE ACIE AC IRQ ACF ACOPE ACMPO ACOPE ACMOD1 ACMOD0 Freescale Semiconductor ...
Page 153
... The ACMP module is capable of generating an interrupt on a compare event. The interrupt request is asserted when both the ACIE bit and the ACF bit are set. The interrupt is deasserted by clearing either the MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Table 9-1. ACMPSC Field Descriptions Description ...
Page 154
... Analog Comparator (S08ACMPVLPV1) ACIE bit or the ACF bit. The ACIE bit is cleared by writing a logic zero and the ACF bit is cleared by writing a logic one. MC9S08LL64 MCU Series Reference Manual, Rev. 6 154 Freescale Semiconductor ...
Page 155
... EREFSTEN. To disable the oscillator in stop2, switch the ICS into FBI or FEI mode before executing the STOP instruction. Figure 10-1 shows the MC9S08LL64 Series block diagram with the ICS highlighted. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Table 4-5. 155 ...
Page 156
... PTA4/KBIP4/ADP8/LCD43 PTA3/KBIP3/SCL/MOSI/ADP7 PTA2/KBIP2/SDA/MISO/ADP6 PTA1/KBIP1/SPSCK/ADP5 PTA0/KBIP0/SS/ADP4 PTB7/TxD2/SS PTB6/RxD2/SPSCK PTB5/MOSI/SCL PTB4/MISO/SDA ∞ PTB2/RESET PTB1/XTAL PTB0/EXTAL PTC7/IRQ/TCLK ◊ PTC6/ACMPO//BKGD/MS PTC5/TPM2CH1 PTC4/TPM2CH0 PTC3/TPM1CH1 PTC2/TPM1CH0 PTC1/TxD1 PTC0/RxD1 • ADP0 • • ADP12 • PTD[7:0]/LCD[7:0] PTE[7:0]/LCD[13:20] and V for the 64-pin DDA SSA Freescale Semiconductor ...
Page 157
... Three selectable digitally-controlled oscillators (DCO) optimized for different frequency ranges. • Option to maximize output frequency for a 32768 Hz external reference clock source. 10.1.4 Block Diagram Figure 10-2 is the ICS block diagram. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Internal Clock Source (S08ICSV3) 157 ...
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... FLL. MC9S08LL64 MCU Series Reference Manual, Rev. 6 158 STOP ERCLKEN EREFS IRCLKEN EREFSTEN DCOOUT LP FLL DCOL Filter DCOM DCOH IREFS DMX32 DRS Internal Clock Source Block l (FEI) (FEE) l (FBI) OSCOUT ICSERCLK ICSIRCLK CLKS BDIV ICSOUT n=0-3 ICSDCLK ICSLCLK / 2 ICSFFCLK Freescale Semiconductor ...
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... ICS registers. Name 7 R ICSC1 CLKS W R ICSC2 BDIV W R ICSTRM W MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor l Low Power (FBILP) l (FBE) l Low Power (FBELP) NOTE Table 10-1. ICS Register Summary RDIV RANGE HGO LP TRIM Internal Clock Source (S08ICSV3) ...
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... MC9S08LL64 MCU Series Reference Manual, Rev. 6 160 IREFST DMX32 5 4 RDIV 0 0 Figure 10-3. ICS Control Register 1 (ICSC1) Description Table 10-3 for the divide-by factors. Table 10-3. Reference Divide Factor RDIV RANGE=0 RANGE CLKST OSCINIT IREFS IRCLKEN IREFSTEN 128 256 Freescale Semiconductor 0 FTRIM 0 0 ...
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... MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Table 10-3. Reference Divide Factor RDIV RANGE=0 RANGE 1024 6 64 Reserved 7 128 Reserved 1 Reset default Internal Clock Source (S08ICSV3) 512 161 ...
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... Reset: Note: TRIM is loaded during reset from a factory programmed location when not in BDM mode BDM mode, a default value of 0x80 is loaded. MC9S08LL64 MCU Series Reference Manual, Rev. 6 162 5 4 RANGE HGO 0 0 Figure 10-4. ICS Control Register 2 (ICSC2) Description 5 4 TRIM Figure 10-5. ICS Trim Register (ICSTRM EREFS ERCLKEN EREFSTEN Freescale Semiconductor ...
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... Internal Reference Status — The IREFST bit indicates the current source for the reference clock. The IREFST IREFST bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock domains. 0 Source of reference clock is external clock. 1 Source of reference clock is internal clock. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Description IREFST CLKST ...
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... Table 10-7. DCO frequency range Reference range FLL factor 31.25 - 39.0625 kHz 512 32.768 kHz 608 31.25 - 39.0625 kHz 1024 32.768 kHz 1216 31.25 - 39.0625 kHz 1536 32.768 kHz 1824 Reserved 1 DCO range MHz 19.92 MHz MHz 39.85 MHz MHz 59.77 MHz Freescale Semiconductor ...
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... The FLL loop locks the frequency to the FLL factor times the internal reference frequency. The ICSLCLK is available for BDC communications, and the internal reference clock is enabled. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor IREFS=1 CLKS=00 FLL Engaged ...
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... CLKS bits are written to 10. • IREFS bit is written to 0. • RDIV bits are written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz. • BDM mode is active or LP bit is written to 0. MC9S08LL64 MCU Series Reference Manual, Rev. 6 166 Freescale Semiconductor ...
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... DCO the FLL remains unlocked for several reference cycles. Once the selected DCO startup time is over, the FLL is locked. The completion of the switch is shown by the DRST bits. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Internal Clock Source (S08ICSV3) 167 ...
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... All MCU devices are factory programmed with a trim value in a reserved memory location. This value is uploaded to the ICSTRM register and ICS FTRIM register during any reset initialization. For finer precision, trim the internal oscillator in the application and set the FTRIM bit accordingly. MC9S08LL64 MCU Series Reference Manual, Rev. 6 168 chapter). Freescale Semiconductor ...
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... The ICS presents the low range DCO output clock divided by two as ICSLCLK for use as a clock source for BDC communications. ICSLCLK is not available in FLL bypassed internal low power (FBILP) and FLL bypassed external low power (FBELP) modes. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Internal Clock Source (S08ICSV3) Device Overview 169 ...
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... Internal Clock Source (S08ICSV3) MC9S08LL64 MCU Series Reference Manual, Rev. 6 170 Freescale Semiconductor ...
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... The ADC, if enabled, must be configured to use the asynchronous clock source, ADACK, to meet the ADC minimum frequency requirements. The VREF output must be enabled in order to convert the bandgap channel in stop mode. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor and V pins. On the 64-pin package, the V REFH ...
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... VLL1 AD25 Reserved AD26 Temperature 1 Sensor AD27 Internal Bandgap AD28 Reserved V V REFH REFH V V REFL REFL Module None Disabled Chapter 10, “Internal Clock Freescale Semiconductor N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A ...
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... TEMP25 11.2 MC9S08LL64 Series Block Diagram Figure 11-1 shows the MC9S08LL64 series with the ADC module highlighted. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor ) ÷ m) Temp = 25 - ((V -V TEMP TEMP25 and m values in the data sheet. TEMP25 ...
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... PTA4/KBIP4/ADP8/LCD43 PTA3/KBIP3/SCL/MOSI/ADP7 PTA2/KBIP2/SDA/MISO/ADP6 PTA1/KBIP1/SPSCK/ADP5 PTA0/KBIP0/SS/ADP4 PTB7/TxD2/SS PTB6/RxD2/SPSCK PTB5/MOSI/SCL PTB4/MISO/SDA ∞ PTB2/RESET PTB1/XTAL PTB0/EXTAL PTC7/IRQ/TCLK ◊ PTC6/ACMPO//BKGD/MS PTC5/TPM2CH1 PTC4/TPM2CH0 PTC3/TPM1CH1 PTC2/TPM1CH0 PTC1/TxD1 PTC0/RxD1 • ADP0 • • ADP12 • PTD[7:0]/LCD[7:0] PTE[7:0]/LCD[13:20] and V for the 64-pin DDA SSA Freescale Semiconductor ...
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... Selectable asynchronous hardware conversion trigger with hardware channel select • Automatic compare with interrupt for less-than, greater-than or equal-to programmable value • Temperature sensor 11.2.2 Block Diagram Figure 11-2 provides a block diagram of the ADC module. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Analog-to-Digital Converter (S08ADC12V2) 175 ...
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... Figure 11-2. ADC Block Diagram Table 11-2. Signal Properties Name Function AD27–AD0 Analog Channel inputs V High reference voltage REFH V Low reference voltage REFL V Analog power supply DDA V Analog ground SSA Async Clock Gen ADACK Bus Clock ÷2 ALTCLK AIEN 1 Interrupt COCO 2 3 Freescale Semiconductor ...
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... This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1 aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other than all 1s) MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor ) DDA as its power connection. In some packages, V ...
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... MC9S08LL64 MCU Series Reference Manual, Rev. 6 178 Description Table 11-4. Input Channel Select Input Select AD0–15 AD16–27 Reserved V REFH V REFL Module disabled ADCH ADCH 00000–01111 10000–11011 11100 11101 11110 11111 Freescale Semiconductor ...
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... Conversion Mode Selection - MODE bits are used to select between the ADC resolution mode. See MODE 1:0 Input Clock Select - ADICLK bits select the input clock source to generate the internal clock ADCK. See ADICLK Table 11-8. MODE 00 01 MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor ADIV ADLSMP Description Table 11-6. Clock Divide Select ...
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... MC9S08LL64 MCU Series Reference Manual, Rev. 6 180 Table 11-7. Conversion Modes (continued) Conversion Mode Description single-ended 10-bit conversion Reserved Table 11-8. Input Clock Select ADICLK Selected Clock Source 00 Bus clock 01 Bus clock divided Alternate clock (ALTCLK) 11 Asynchronous clock (ADACK ADACKEN Description ADHSC ADLSTS 0 0 Freescale Semiconductor 0 0 ...
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... In 8-bit single-ended mode, there is no interlocking with ADCRL Reset Figure 11-6. Data Result High Register (ADCRH Reset Figure 11-7. Data Result Low Register (ADCRL) MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Description D[7: Analog-to-Digital Converter (S08ADC12V2 ...
Page 182
... This register holds the lower 8 bits of the 12-bit or 10-bit compare value or all 8 bits of the 8-bit compare value. Bits ADCV7:ADCV0 are compared to the lower 8 bits of the result following a conversion in 12-bit, 10-bit or 8-bit mode. MC9S08LL64 MCU Series Reference Manual, Rev. 6 182 DATA Format D D unsigned right justified D D unsigned right justified D D unsigned right justified CV[11: Freescale Semiconductor 0 0 ...
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... Compare triggers when input is less than compare level 1 Compare triggers when input is greater than or equal to compare level. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor ...
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... AD7 pin I/O control disabled 6 ADC Pin Control 6 - ADPC6 controls the pin associated with channel AD6. ADPC6 0 AD6 pin I/O control enabled 1 AD6 pin I/O control disabled MC9S08LL64 MCU Series Reference Manual, Rev. 6 184 ADCO Description ADPC[7: Description Section 11.5.4.1 for more Freescale Semiconductor ...
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... AD14 pin I/O control enabled 1 AD14 pin I/O control disabled 5 ADC Pin Control 13 - ADPC13 controls the pin associated with channel AD13. ADPC13 0 AD13 pin I/O control enabled 1 AD13 pin I/O control disabled MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Description ADPC[15: ...
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... AD21 pin I/O control enabled 1 AD21 pin I/O control disabled 4 ADC Pin Control 20 - ADPC20 controls the pin associated with channel AD20. ADPC20 0 AD20 pin I/O control enabled 1 AD20 pin I/O control disabled MC9S08LL64 MCU Series Reference Manual, Rev. 6 186 Description ADPC[23:16 Description Freescale Semiconductor ...
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... Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the available clocks are too slow, the ADC may not perform according to specifications. If the available clocks MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Analog-to-Digital Converter (S08ADC12V2) Description for more information ...
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... Following the transfer of the result to the data registers when continuous conversion is enabled (ADCO=1). If continuous conversions are enabled, a new conversion is automatically initiated after the completion of the current conversion. In software triggered operation (ADTRG=0), continuous conversions begin after MC9S08LL64 MCU Series Reference Manual, Rev. 6 188 Freescale Semiconductor ...
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... When a conversion is aborted, the contents of the data registers, ADCRH and ADCRL are not altered. The data registers continue to be the values transferred after the completion of the last successful conversion. If the conversion was aborted by a reset or stop2, ADCRH:ADCRL return to their reset states. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Analog-to-Digital Converter (S08ADC12V2) NOTE 189 ...
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... MC9S08LL64 MCU Series Reference Manual, Rev. 6 190 ). f ADCK frequency, precise sample time for continuous conversions ADCK Conversion Time Equation ( = + + SFCAdder BCT LSTAdder Single or First Continuous Time Adder (SFCAdder) 0x ADCK cycles + 5 bus clock cycles Table 11-18 through Table 11-21 Eqn. 11 HSCAdder Freescale Semiconductor ...
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... Table 11-18. Long Sample Time Adder (LSTAdder MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Single or First Continuous Time Adder (SFCAdder ADCK cycles + 5 bus clock cycles 11 5μ ADCK cycles + 5 bus clock cycles 0x ADCK cycles + 5 bus clock cycles ...
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... Table 11-20. Typical Conversion Time Time 5 ADCK cycles + 5 bus clock cycles 20 ADCK cycles 0 0 and the information provided in Equation 11-3. ADCK Table 11-18 through through Table 11-21. The following Table 11-22. So for Bus clock Table 11-18 through Table 11-21. The Freescale Semiconductor ...
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... The ADC module includes a temperature sensor whose output is connected to one of the ADC analog channel inputs. Equation 11-3 provides an approximate transfer function of the temperature sensor. where: MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Table 11-21. Typical Conversion Time Time 5 ADCK cycles + 5 bus clock cycles 17 ADCK cycles 0 ADCK cycles 4 Table 11-22 ...
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... ADCRH and ADCRL, are unaffected by stop3 mode. After exiting from stop3 mode, a software or hardware trigger is required to resume conversions. MC9S08LL64 MCU Series Reference Manual, Rev. 6 194 and m values from the ADC Electricals table. TEMP25 , the cold slope value is applied in Equation 11-3. , and compare to V TEMP TEMP25. Equation 11- less than TEMP Freescale Semiconductor ...
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... Table 11-8 for information used in this example. Hexadecimal values designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Analog-to-Digital Converter (S08ADC12V2) NOTE Conversions) is cleared when entering stop3 NOTE ...
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... Not used in this example. Reserved, always reads zero. Reserved for Freescale’s internal use; always write zero. Read-only flag which is set when a conversion completes. Conversion complete interrupt enabled. One conversion only (continuous conversions disabled). Input channel 1 selected as ADC input channel. Freescale Semiconductor ...
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... Analog Supply Pins The ADC module has analog power and ground supplies (V some devices shared on the same pin as the MCU digital V SSA MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Analog-to-Digital Converter (S08ADC12V2) Reset Initialize ADC ADCCFG = 0x98 ADCSC2 = 0x00 ADCSC1 = 0x41 ...
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... The best external component to meet this REFH REFL Setting the pin control register bits for all pins used SSA and V REFH on some devices. The low DDA on some devices may be DDA potential (V must never DDA REFH . If the input is equal to or REFL Freescale Semiconductor ...
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... For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces V noise but increases effective conversion time due to stop recovery. • There is no I/O switching, input or output, on the MCU during the conversion. MC9S08LL64 MCU Series Reference Manual, Rev. 6 Freescale Semiconductor Analog-to-Digital Converter (S08ADC12V2) REFH when the sampling REFL ...
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... Differential non-linearity (DNL) — This error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions. MC9S08LL64 MCU Series Reference Manual, Rev. 6 200 ) on the selected input channel lsb = ( REFH REFL or V (this improves REFL SSA , one-time error. LSB Eqn. 11-4 in 12-bit LSB Freescale Semiconductor ...