R5F211B4DD#ES Renesas Electronics America, R5F211B4DD#ES Datasheet - Page 19
![MCU 3/5V 16K PB-FREE 20-SDIP ES](/photos/12/26/122692/r5f21181dd_u0_sml.jpg)
R5F211B4DD#ES
Manufacturer Part Number
R5F211B4DD#ES
Description
MCU 3/5V 16K PB-FREE 20-SDIP ES
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/1Br
Datasheet
1.R5F211A2SPU0.pdf
(51 pages)
Specifications of R5F211B4DD#ES
Core Processor
R8C
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
For Use With
R0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
R8C/1A Group, R8C/1B Group
Rev.1.40
REJ03B0144-0140
2.8.7
2.8.8
2.8.9
2.8.10
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I
flag is set to 0 when an interrupt request is acknowledged.
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of
software interrupt numbers 0 to 31 is executed.
IPL is 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
If necessary, set to 0. When read, the content is undefined.
Dec 08, 2006
Interrupt Enable Flag (I)
Stack Pointer Select Flag (U)
Processor Interrupt Priority Level (IPL)
Reserved Bit
Page 17 of 45
2. Central Processing Unit (CPU)