MC908AP32ACFBE Freescale Semiconductor, MC908AP32ACFBE Datasheet - Page 289
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MC908AP32ACFBE
Manufacturer Part Number
MC908AP32ACFBE
Description
IC MCU 32K FLASH 8MHZ 44-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AP16ACFBER.pdf
(316 pages)
Specifications of MC908AP32ACFBE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFP
Controller Family/series
HC08
No. Of I/o's
32
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08AP
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908AP64E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Chapter 21
Break Module (BRK)
21.1 Introduction
This section describes the break module. The break module can generate a break interrupt that stops
normal program flow at a defined address to enter a background program.
21.2 Features
Features of the break module include:
21.3 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal to the SIM. The SIM then causes the CPU to load the instruction register with
a software interrupt instruction (SWI) after completion of the current CPU instruction. The program
counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
Freescale Semiconductor
Note: Writing a logic 0 clears BW.
$FE0C
$FE0D
$FE00
$FE03
$FE0E
Addr.
•
•
•
•
Accessible input/output (I/O) registers during the break interrupt
CPU-generated break interrupts
Software-generated break interrupts
COP disabling during break interrupts
SIM Break Status Register
Break Status and Control
SIM Break Flag Control
Register Name
Break Address
Break Address
Register High
Register Low
(BRKSCR)
(SBFCR)
Register
Register
(BRKH)
(SBSR)
(BRKL)
Figure 21-1. Break Module I/O Register Summary
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
MC68HC908AP A-Family Data Sheet, Rev. 3
BRKE
BCFE
Bit 15
Bit 7
Bit 7
R
0
0
0
0
= Unimplemented
BRKA
14
R
R
6
0
6
0
0
13
R
R
5
0
5
0
0
0
12
R
R
R
4
0
4
0
0
0
= Reserved
11
R
R
3
0
3
0
0
0
10
R
R
2
0
2
0
0
0
SBSW
Note
R
1
0
9
0
1
0
0
0
Bit 0
Bit 8
Bit 0
R
R
0
0
0
0
289
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