C8051F045-GQR Silicon Laboratories Inc, C8051F045-GQR Datasheet - Page 242
C8051F045-GQR
Manufacturer Part Number
C8051F045-GQR
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F045-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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19.2.2. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.
19.2.3. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,
the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-
cation no later than 10 ms after detecting the timeout condition.
19.2.4. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. If an SMBus device is waiting to generate a Master START, the START will be gen-
erated following the bus free timeout.
19.3. SMBus Transfer Modes
The SMBus0 interface may be configured to operate as a master and/or a slave. At any particular time, the
interface will be operating in one of the following modes: Master Transmitter, Master Receiver, Slave
Transmitter, or Slave Receiver. See Table 19.1 for transfer mode status decoding using the SMB0STA sta-
tus register. The following mode descriptions illustrate an interrupt-driven SMBus0 application; SMBus0
may alternatively be operated in polled mode.
19.3.1. Master Transmitter Mode
Serial data is transmitted on SDA while the serial clock is output on SCL. SMBus0 generates a START
condition and then transmits the first byte containing the address of the target slave device and the data
direction bit. In this case the data direction bit (R/W) will be logic 0 to indicate a "WRITE" operation. The
SMBus0 interface transmits one or more bytes of serial data, waiting for an acknowledge (ACK) from the
slave after each byte. To indicate the end of the serial transfer, SMBus0 generates a STOP condition.
242
Interrupt
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 19.4. Typical Master Transmitter Sequence
SLA
W
Interrupt
A
Data Byte
Rev. 1.5
Interrupt
A
2
C, which allows devices with different
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Data Byte
Interrupt
A
P
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