R5F212A8SNFA#U0 Renesas Electronics America, R5F212A8SNFA#U0 Datasheet - Page 608

• Manufacturer Part Number: R5F212A8SNFA#U0
• Description: IC R8C/2A MCU FLASH 64K 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Ar

Specifications of R5F212A8SNFA#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
2.00
REVISION HISTORY
Nov 26, 2007
Date
191 to 194 14.2.5.1, 14.2.5.2, 14.2.5.3, 14.2.5.4 added
Page
183
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Table 14.10 Count stop conditions:
14.2.5 NOTE TRBIOC added
Figure 14.37 TRCIOR0: b3 revised, NOTE4 added
14.3.4 “The TRCGRA register can .... input-capture trigger input.” added
Table 14.17 revised
Figure 14.43 revised
Figure 14.44 b3 revised, NOTE3 added
Table 14.19 Select functions:
Figure 14.48 b3 revised
Figure 14.51 “• The CCLR bit in the TRCCR1 register is set to 0 ....”
Figure 14.88 TRDOER1 revised
Figure 14.93 revised
Figure 14.99 revised
Figure 14.107 revised
Figure 14.116 “TRD” → “TRD0”
Figure 14.120 revised
Figure 14.123 NOTE1 revised
Figure 14.127 b0, b1 revised
Figure 14.128 “TRD” → “TRD0”
Figure 14.132 revised
Figure 14.140 revised
Figure 14.146 revised
Figure 14.150 “TSTP0 bit in TRDSTR register” → “CSEL0 bit in
Figure 14.164 b0, b1: “Set to 00 in real-time clock mode.” → “Set to 00b
Figure 14.173 revised
Figure 14.179 NOTE4 added
Figure 15.4 UARTi Transmit/Receive Mode Register revised
Figure 15.7 After Reset: “00h” → “000000XXb”, b1-b0 revised
Table 15.5 NOTE2 added
Figure 16.3 NOTE4 deleted
Figure 16.4 SOLP: “Cannot w rite to this.” → “The SOLP bit remains
Figure 16.5 NOTE2 deleted
R8C/2A Group, R8C/2B Group Hardware Manual
“• When the TOSSP .... is set to 0 (one-shot stops).”
→ “• When the TOSSP .... is set to 1 (one-shot stops).”
unchanged even if 1 is written to it.”, NOTE4 deleted
“or output level inverted” → “or toggle output”
→ “• The CCLR bit in the TRCCR1 register is set to 1 ....”
TRDSTR register”
in real-time clock mode.”
C - 6
Description
Summary