R5F2L387ANFP#U1 Renesas Electronics America, R5F2L387ANFP#U1 Datasheet - Page 595

• Manufacturer Part Number: R5F2L387ANFP#U1
• Description: MCU 1KB FLASH 48K ROM 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/38Ar

Specifications of R5F2L387ANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 68
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 558 of 802
26.3
26.3.1
26.3.1.1
The transfer clock can be selected from among seven internal clocks (f1/256, f1/128, f1/64, f1/32, f1/16, f1/8,
and f1/4) and an external clock.
To use the synchronous serial communication unit, set the SCKS bit in the SSMR2 register to 1 and select the
SSCK pin as the serial clock pin.
When the MSS bit in the SSCRH register is set to 1 (operation as the master device), an internal clock can be
selected and the SSCK pin functions as output. When transfer is started, the SSCK pin outputs a clock at the
transfer rate selected by bits CKS0 to CKS2 in the SSCRH register.
When the MSS bit in the SSCRH register is set to 0 (operation as a slave device), an external clock can be
selected and the SSCK pin functions as input.
The association between the transfer clock polarity, phase, and data changes according to the combination of
the SSUMS bit in the SSMR2 register and bits CPHS and CPOS in the SSMR register.
Figure 26.2 shows the Association between Transfer Clock Polarity, Phase, and Transfer Data.
Also, the MSB-first transfer or LSB-first transfer can be selected by setting the MLS bit in the SSMR register.
When the MLS bit is set to 1, transfer is started from the LSB and proceeds to the MSB. When the MLS bit is
set to 0, transfer is started from the MSB and proceeds to the LSB.
Common Items for Multiple Modes
Transfer Clock
Association between Transfer Clock Polarity, Phase, and Data
Oct 30, 2009
26. Synchronous Serial Communication Unit (SSU)