C8051F047-GQ Silicon Laboratories Inc, C8051F047-GQ Datasheet - Page 249
![IC 8051 MCU 32K FLASH 64TQFP](/photos/12/37/123767/c8051f047-gq_sml.jpg)
C8051F047-GQ
Manufacturer Part Number
C8051F047-GQ
Description
IC 8051 MCU 32K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F047-GQ
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F040DK
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1212
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F047-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F047-GQR
Manufacturer:
MAXIM
Quantity:
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Company:
Part Number:
C8051F047-GQR
Manufacturer:
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Quantity:
10 000
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19.4.3. Data Register
The SMBus0 Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just
been received. Software can read or write to this register while the SI flag is set to logic 1; software should
not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag reads logic 0
since the hardware may be in the process of shifting a byte of data in or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. Therefore, SMB0DAT always contains the last data byte present on the bus. In the event
of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in
SMB0DAT.
19.4.4. Address Register
The SMB0ADR Address register holds the slave address for the SMBus0 interface. In slave mode, the
seven most-significant bits hold the 7-bit slave address. The least significant bit (Bit0) is used to enable the
recognition of the general call address (0x00). If Bit0 is set to logic 1, the general call address will be recog-
nized. Otherwise, the general call address is ignored. The contents of this register are ignored when
SMBus0 is operating in master mode.
Bits7-0:
R/W
Bit7
SMB0DAT: SMBus0 Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus0 serial inter-
face or a byte that has just been received on the SMBus0 serial interface. The CPU can
read from or write to this register whenever the SI serial interrupt flag (SMB0CN.3) is set to
logic 1. When the SI flag is not set, the system may be in the process of shifting data and the
CPU should not attempt to access this register.
R/W
Bit6
SFR Definition 19.3. SMB0DAT: SMBus0 Data
R/W
Bit5
R/W
Bit4
Rev. 1.5
R/W
Bit3
C8051F040/1/2/3/4/5/6/7
R/W
Bit2
R/W
Bit1
SFR Address:
SFR Page:
R/W
Bit0
0xC2
0
00000000
Reset Value
249
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