C8051F047-GQ Silicon Laboratories Inc, C8051F047-GQ Datasheet - Page 98
![IC 8051 MCU 32K FLASH 64TQFP](/photos/12/37/123767/c8051f047-gq_sml.jpg)
C8051F047-GQ
Manufacturer Part Number
C8051F047-GQ
Description
IC 8051 MCU 32K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F047-GQ
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F040DK
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1212
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F047-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F047-GQR
Manufacturer:
MAXIM
Quantity:
18
Company:
Part Number:
C8051F047-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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C8051F040/1/2/3/4/5/6/7
98
Bit7:
Bit6:
Bit5:
Bit4:
Bits3-1:
Bit0:
An important note about external convert start (CNVSTR0 and CNVSTR2): If CNVSTR2 is enabled in
AD2EN
R/W
Bit7
AD2EN: ADC2 Enable Bit.
0: ADC2 Disabled. ADC2 is in low-power shutdown.
1: ADC2 Enabled. ADC2 is active and ready for data conversions.
AD2TM: ADC2 Track Mode Bit.
0: Normal Track Mode: When ADC2 is enabled, tracking is continuous unless a conversion is in
process.
1: Low-power Track Mode: Tracking defined by AD2CM2-0 bits (see below).
AD2INT: ADC2 Conversion Complete Interrupt Flag.
This flag must be cleared by software.
0: ADC2 has not completed a data conversion since the last time this flag was cleared.
1: ADC2 has completed a data conversion.
AD2BUSY: ADC2 Busy Bit.
Read:
0: ADC2 Conversion is complete or a conversion is not currently in progress. AD2INT is set to
logic 1 on the falling edge of AD2BUSY.
1: ADC2 Conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC2 Conversion if AD2CM2-0 = 000b
AD2CM2-0: ADC2 Start of Conversion Mode Select.
AD2TM = 0:
000: ADC2 conversion initiated on every write of ‘1’ to AD2BUSY.
001: ADC2 conversion initiated on overflow of Timer 3.
010: ADC2 conversion initiated on rising edge of external CNVSTR2 or CNVSTR0.
011: ADC2 conversion initiated on overflow of Timer 2.
1xx: ADC2 conversion initiated on write of ‘1’ to AD0BUSY (synchronized with ADC0 software-
commanded conversions).
AD2TM = 1:
000: Tracking initiated on write of ‘1’ to AD2BUSY and lasts 3 SAR2 clocks, followed by conver-
sion.
001: Tracking initiated on overflow of Timer 3 and lasts 3 SAR2 clocks, followed by conversion.
010: ADC2 tracks only when CNVSTR2 (or CNVSTR0, See Section 7.2.1) input is logic low; con-
version starts on rising CNVSTR2 edge.
011: Tracking initiated on overflow of Timer 2 and lasts 3 SAR2 clocks, followed by conversion.
1xx: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR2 clocks, followed by conver-
sion.
AD2WINT: ADC2 Window Compare Interrupt Flag.
0: ADC2 window comparison data match has not occurred since this flag was last cleared.
1: ADC2 window comparison data match has occurred. This flag must be cleared in software.
the digital crossbar (
on page 204
CNVSTR0 is enabled in the digital crossbar and CNVSTR2 is not enabled, then CNVSTR0 may
serve as the start of conversion for both ADC0 and ADC2.
AD2TM
R/W
Bit6
SFR Definition 7.4. ADC2CN: ADC2 Control
AD2INT AD2BUSY AD2CM2 AD2CM1
), CNVSTR2 will be the external convert start signal for ADC2. However, if only
R/W
Bit5
Section “17.1. Ports 0 through 3 and the Priority Crossbar Decoder”
R/W
Bit4
Rev. 1.5
R/W
Bit3
R/W
Bit2
AD2CM0
R/W
Bit1
SFR Address:
AD2WINT 00000000
SFR Page:
R/W
Bit0
0xE8
2
Reset Value
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