C8051F044-GQR Silicon Laboratories Inc, C8051F044-GQR Datasheet - Page 220
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C8051F044-GQR
Manufacturer Part Number
C8051F044-GQR
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F044-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F044-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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C8051F040/1/2/3/4/5/6/7
17.2. Ports 4 through 7
On C8051F040/2/4/6 devices, all Port pins on Ports 4 through 7 can be accessed as General-Purpose I/O
(GPIO) pins by reading and writing the associated Port Data registers (See SFR Definition 17.16, SFR
Definition 17.18, SFR Definition 17.20, and SFR Definition 17.22 located on SFR Page F), a set of SFRs
which are both bit and byte-addressable.
A Read of a Port Data register (or Port bit) will always return the logic state present at the pin itself, regard-
less of whether the Crossbar has allocated the pin for peripheral use or not. An exception to this occurs
during the execution of a read-modify-write instruction (ANL, ORL, XRL, CPL, INC, DEC, DJNZ, JBC,
CLR, SET, and the bitwise MOV operation). During the read cycle of the read-modify-write instruction, it is
the contents of the Port Data register, not the state of the Port pins themselves, which is read.
220
Bits7-0:
Bits7-0:
R/W
R/W
Bit7
Bit7
P1MDIN.[7:0]: Port 3 Input Mode Bits.
0: Port Pin is configured in Analog Input mode. The digital input path is disabled (a read from
the Port bit will always return ‘0’). The weak pullup on the pin is disabled.
1: Port Pin is configured in Digital Input mode. A read from the Port bit will return the logic
level at the Pin. The state of the weak pullup is determined by the WEAKPUD bit (XBR2.7,
see SFR Definition 17.3).
P2MDOUT.[7:0]: Port3 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
R/W
R/W
Bit6
Bit6
SFR Definition 17.15. P3MDOUT: Port3 Output Mode
SFR Definition 17.14. P3MDIN: Port3 Input Mode
R/W
R/W
Bit5
Bit5
R/W
R/W
Bit4
Bit4
Rev. 1.5
R/W
R/W
Bit3
Bit3
R/W
R/W
Bit2
Bit2
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
SFR Page:
SFR Page:
R/W
R/W
Bit0
Bit0
0xA7
F
0xAF
F
00000000
Reset Value
Reset Value
11111111
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