MCF5208CVM166J Freescale Semiconductor, MCF5208CVM166J Datasheet

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... MCF5208 device. See the following section for a summary of differences between the two devices. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2009. All rights reserved. ® Table of Contents 1 MCF5207/8 Device Configurations ...

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... QFP 196 MAPBGA Speed Temperature ° to +85 166.67 MHz –40 ° to +85 166.67 MHz –40 ° to +85 166.67 MHz –40 ° to +85 166.67 MHz –40 Freescale Semiconductor ° C ° C ° C ° C ...

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... RCON — DRAMSEL — A[23:22] — FB_CS[5:4] A[21:16] — A[15:14] — SD_BA[1:0] A[13:11] — SD_A[13:11] A10 — MCF5208 ColdFire Freescale Semiconductor Section 4, “Mechanicals and Pinouts” NOTE NOTE Alternate 2 Reset — — I EVDD — — O EVDD Clock — — I EVDD — ...

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... D7, A9 — 121 C8 127 122 B8 128 19, 49 F3 Freescale Semiconductor MCF5208 196 MAPBGA E13, E14, F11–F14, G11–G14 J4–J1, K4–K1, M3, N3, M4, N4, P4, L5, M5, N5 F3–F1, G4–G1, H1, N6, P6, L7, M7, N7, P7, N8, P8 H2, P5, H4 H14 L8 E3 C11, A10 B10 C10 H3 ...

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... I2C_SDA PFECI2C0 U2RXD 2 2 I2C_SCL PFECI2C1 U2TXD DACK0 and DREQ0 do not have a dedicated bond pads. Please refer to the following pins for muxing: TS and QSPI_CS2 for DACK0, IRQ4 and QSPI_DIN for DREQ0. Freescale Semiconductor Alternate 2 External Interrupts Port — — I EVDD 2 — I EVDD — ...

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... C5 144 137 A4 145 138 A3 146 83 J11 91 76 K11 L12 — K9, L9, M11, — M8 — L11, L8, — K10, K8 Freescale Semiconductor MCF5208 196 MAPBGA D10 N12 P12 P13 N13 J13 L12 P9 M14 K12 M12 P11, N11, M11, P10 N10, M10, L10, L9 ...

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... GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins. 7 Pull-down enabled internally on this signal for this mode. Freescale Semiconductor Alternate 2 — — O EVDD Test — ...

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... Microprocessor Data Sheet, Rev. 3 108 A17 107 A16 106 A15 105 A14 104 A13 103 A12 102 A11 101 A10 100 SD_VDD 88 VSS 87 EVDD 86 PLL_VDD 85 PLL_VSS 84 IVDD 83 JTAG_EN 82 RESET 81 EVDD 80 XTAL 79 DRAMSEL 78 EXTAL 77 TDI/DSI 76 TRST/DSCLK 75 TMS/BKPT 74 RSTOUT 73 VSS Freescale Semiconductor ...

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... Package Dimensions—144 LQFP Figure 2 and Figure 3 show MCF5207CAB166 package dimensions. Figure 2. MCF5207CAB166 Package Dimensions (Sheet MCF5208 ColdFire Freescale Semiconductor ® Microprocessor Data Sheet, Rev. 3 Mechanicals and Pinouts 9 ...

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... Mechanicals and Pinouts View A Figure 3. MCF5207CAB166 Package Dimensions (Sheet MCF5208 ColdFire 10 Section A-A Rotated 90× CW 144 Places View B ® Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor ...

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... SD_CLK SD_RAS SD_VDD K SD_CLK D20 D23 L FB_CLK D22 D21 BE/BWE2 M SD_A10 SD_CAS D19 Figure 4. MCF5207CVM166 Pinout Top View (144 MAPBGA) MCF5208 ColdFire Freescale Semiconductor QSPI_ IRQ7 U1TXD QSPI_CS2 DOUT QSPI_ DT3IN IRQ1 DIN QSPI_ DT2IN IRQ4 CLK IVDD U0RTS U1RXD FB_CS3 ...

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... Mechanicals and Pinouts 4.4 Package Dimensions—144 MAPBGA Figure 5 shows the MCF5207CAB166 package dimensions. Figure 5. MCF5207CAB166 Package Dimensions (144 MAPBGA) MCF5208 ColdFire 12 ® Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor ...

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... D25 33 D24 34 SD_SDR_DQS 35 IVDD 36 SD_CLK 37 SD_CLK 38 SD_VDD 39 FB_CLK 40 Figure 6. MCF5208CAB166 Pinout Top View (160 QFP) MCF5208 ColdFire Freescale Semiconductor ® Microprocessor Data Sheet, Rev. 3 Mechanicals and Pinouts 120 A18 119 VSS 118 SD_VDD 117 VSS 116 A17 115 A16 114 A15 ...

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... Mechanicals and Pinouts 4.6 Package Dimensions—160 QFP The package dimensions of the MCF5208CAB166 device are shown in the figures below. Figure 7. MCF5208CAB166 Package Dimensions (Sheet MCF5208 ColdFire 14 Top View ® Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor ...

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... DETAIL A Figure 8. MCF5208CAB166 Package Dimensions (Sheet MCF5208 ColdFire Freescale Semiconductor SECTION B-B ® Microprocessor Data Sheet, Rev. 3 Mechanicals and Pinouts 15 ...

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... EVDD EVDD EVDD SEL DSI TRST/ PST0 PST1 IVDD VSS DSCLK TDO/ PLL_ EVDD PST2 DDATA1 DSO TEST VSS PST3 DDATA2 U0CTS U0RXD TCLK/ DDATA0 DDATA3 U0RTS U0TXD Freescale Semiconductor 13 14 VSS A A17 B A15 C A12 RESET J EN XTAL K EXTAL L TMS/ M BKPT ...

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... Maximum Ratings Rating Core Supply Voltage CMOS Pad Supply Voltage DDR/Memory Pad Supply Voltage PLL Supply Voltage 3 Digital Input Voltage Instantaneous Maximum Current Single pin limit (applies to all pins) MCF5208 ColdFire Freescale Semiconductor Table 4. Absolute Maximum Ratings Symbol SDV DD PLLV DD V ...

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... Microprocessor Data Sheet, Rev. 3 (continued) °C – °C – 150 range during instantaneous > greater in DD range during DD 1,2 1,2 1,2 1 1,2 1,2 1,2 1 1,5 1,6 1 105 105 105 Freescale Semiconductor ° ° ° ° ° ...

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... T D solving Equation 1 and Equation 2 5.3 ESD Protection Characteristics ESD Target for Human Body Model NOTES: 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. MCF5208 ColdFire Freescale Semiconductor ) in °C can be obtained from × Θ JMA and can be ignored ...

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... V 1.4 1.6 V 3.0 3 1.70 1.95 2.25 2.75 3 0.3 0 0.4 — — 0 1.35 SDV + 0.3 DD 1.7 SDV + 0 SDV + 0 0.3 0. 0.3 0 0.3 0 SDV - 0.35 — DD 2.1 — 2.4 — V — 0.3 — 0.3 — 0.5 μA –1.0 1.0 Freescale Semiconductor ...

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... Power Down Sequence If IV /PLLV are powered down first, sense circuits in the I/O pads cause all output drivers high impedance state. There is no limit on how long after IV or SDV must power down MCF5208 ColdFire Freescale Semiconductor Symbol 1 Max APU Ω 10 µF 0.1 µ ...

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... MHz 83.33 MHz 10.61 12.1 12.1 2.5 2.61 2.61 16.91 17.24 17.24 10.73 12.25 12.25 2..5 2.6 4.07 16.91 17.24 18.77 15.92 18.21 35.45 19.54 29.12 30.43 16.89 17.23 18.76 23.57 27.0 44.1 power supplies. Tests performed at DD Freescale Semiconductor ...

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... Figure 12. Current Consumption in Low-Power Modes Table 9. Typical Active Current Consumption Specifications f Frequency sys/2 1 MHz 2 MHz 4 MHz 44 MHz 48 MHz MCF5208 ColdFire Freescale Semiconductor 83.33 83.33(peak) fsys/2 (MHz) 2 Typical Active (mA) Voltage (V) SRAM Flash 3.3 2.04 2.12 2.5 15.24 15.32 1 ...

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... IV power DD DD Min. Max. Value Value 488 x 10 166.66 -6 244 x 10 83.33 — 0.4 — XTAL 0.4 — VDD — 0.4 XTAL — 0.4 VDD — 50000 CLKIN 40 60 Freescale Semiconductor Unit MHz MHz MHz MHz ...

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... External Interface Timing Characteristics Table 11 lists processor bus input timings. All processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. The reference clock is the FB_CLK output. MCF5208 ColdFire Freescale Semiconductor Symbol I XTAL C S_XTAL C ...

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... ROM access and can be programmed to be byte (8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM/flash memories. MCF5208 ColdFire 26 are shown in Figure 14 and Figure 1.5V T SETUP T HOLD Invalid 1.5V Valid 1. ® Microprocessor Data Sheet, Rev. 3 15. Invalid t rise t fall FB5 Freescale Semiconductor ...

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... The address and data busses are muxed between the FlexBus and SDRAM controller. At the end of the read and write bus cycles the address signals are indeterminate. MCF5208 ColdFire Freescale Semiconductor Table 11. FlexBus AC Timing Specifications Symbol t FBCK ...

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... FB2 ADDR[31:X] DATA FB_R/W FB_TS FB6 FB_TA Figure 14. FlexBus Read Timing S0 S1 FB_CLK FB1 ADDR[23:0] FB2 ADDR[31:X] DATA FB_R/W FB_TS FB_OE FB6 FB_TA Figure 15. Flexbus Write Timing ® Microprocessor Data Sheet, Rev FB3 FB5 FB4 FB7 S2 S3 FB3 FB7 Freescale Semiconductor ...

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... Because a read cycle in SDR mode continues using the DQS circuit within the device most critical that the data valid window be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup spec is provided as guidance. MCF5208 ColdFire Freescale Semiconductor Table 12. SDR Timing Specifications Symbol t ...

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... WD3 Figure 16. SDR Write Timing SD1 SD5 3/4 MCLK Reference COL tDQS Board Delay Board Delay SD10 Figure 17. SDR Read Timing ® Microprocessor Data Sheet, Rev. 3 SD2 SD3 WD4 SD2 SD3 SD6 SD8 SD7 SD9 WD1 WD2 WD3 WD4 Freescale Semiconductor ...

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... MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0]. 6 The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are valid for each subsequent DQS edge. MCF5208 ColdFire Freescale Semiconductor Table 13. DDR Timing Specifications Symbol — t ...

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... SD_CLK SD_CLK SD_CSn, SD_WE, SD_RAS, SD_CAS DD4 A[13:0] DM3/DM2 SD_DQS3/SD_DQS2 D[31:24]/D[23:16] MCF5208 ColdFire 32 DD1 DD2 DD5 CMD DD6 ROW COL WD1 WD2 WD3 WD4 Figure 18. DDR Write Timing ® Microprocessor Data Sheet, Rev. 3 DD3 DD7 DD8 DD7 DD8 Freescale Semiconductor ...

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... FB_CLK High to GPIO Output Invalid G3 GPIO Input Valid to FB_CLK High G4 FB_CLK High to GPIO Input Invalid NOTES: 1 GPIO spec cover: IRQn, UART and Timer pins. MCF5208 ColdFire Freescale Semiconductor DD1 DD5 CMD DD4 ROW COL Figure 19. DDR Read Timing Table 14. GPIO Timing Characteristic ® ...

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... GPIO Inputs Figure 20. GPIO Timing ® Microprocessor Data Sheet, Rev Symbol Min Max t 9 — RVCH t 1.5 — CHRI t 5 — RIVT t — 10 CHROV t 0 — ROVCV t 20 — COS t 0 — COH t — 1 ROICZ Freescale Semiconductor Unit CYC CYC ns t CYC R8 ...

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... Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load. MCF5208 ColdFire Freescale Semiconductor NOTE 2 C input and output timing parameters. Characteristic = 0 ...

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... FEC_RXCLK (input) FEC_RXD[3:0] (inputs) FEC_RXDV FEC_RXER Figure 23. MII Receive Signal Timing Diagram MCF5208 ColdFire Figure 22 Input/Output Timings Table 18. MII Receive Signal Timing Characteristic Table 18 ® Microprocessor Data Sheet, Rev Min Max Unit 5 — — ns 35% 65% FEC_RXCLK period 35% 65% FEC_RXCLK period M4 Freescale Semiconductor ...

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... Table 20 lists MII asynchronous inputs signal timing. Num M9 FEC_CRS, FEC_COL minimum pulse width Figure 25 shows MII asynchronous input timings listed in FEC_CRS FEC_COL MCF5208 ColdFire Freescale Semiconductor Table 19. MII Transmit Signal Timing Characteristic Table 19 Table 20. MII Async Inputs Signal Timing Characteristic Table M9 Figure 25 ...

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... FEC_MDIO (output) FEC_MDIO (input) Figure 26. MII Serial Management Channel Timing Diagram MCF5208 ColdFire 38 Characteristic Table M14 M10 M11 M12 M13 ® Microprocessor Data Sheet, Rev. 3 Min Max Unit 0 — ns — — — ns 40% 60% FEC_MDC period 40% 60% FEC_MDC period 21. M15 Freescale Semiconductor ...

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... QS4 QSPI_DIN to QSPI_CLK (Input setup) QS5 QSPI_DIN to QSPI_CLK (Input hold) The values in Table 23 correspond to QS1 QSPI_CS[3:0] QSPI_CLK QSPI_DOUT QS3 QSPI_DIN MCF5208 ColdFire Freescale Semiconductor Characteristic Characteristic Figure 27. QS2 Figure 27. QSPI Timing ® Microprocessor Data Sheet, Rev. 3 Electrical Characteristics Unit Min Max 3 — ...

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... Microprocessor Data Sheet, Rev. 3 Symbol Min Max Unit f DC 1/4 f JCYC sys — t JCYC CYC t 26 — ns JCW JCRF t 4 — ns BSDST t 26 — ns BSDHT BSDV BSDZ t 4 — ns TAPBST t 10 — ns TAPBHT TDODV TDODZ t 100 — ns TRSTAT t 10 — ns TRSTST J3 Freescale Semiconductor ...

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... Data Inputs Data Outputs Data Outputs Data Outputs TCLK V IL TDI TMS TDO TDO TDO TCLK TRST MCF5208 ColdFire Freescale Semiconductor Figure 29. Boundary Scan (JTAG) Timing J9 Input Data Valid J11 J12 J11 Figure 30. Test Access Port Timing J14 J13 Figure 31. TRST Timing ® ...

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... Table 25. Debug AC Timing Specification Characteristic Min 1 — 1 Figure 32. Real-Time Trace AC Timing D5 Current D4 Past Figure 33. BDM Serial Port AC Timing ® Microprocessor Data Sheet, Rev. 3 Figure 32. Max Unit 1 t SYS 3.0 ns — ns — PSTCLK — PSTCLK — PSTCLK — PSTCLK D2 Next Current Freescale Semiconductor ...

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... MCF5208 ColdFire Freescale Semiconductor Table 26. Revision History Substantive Changes • Initial Release • Corrected 144QFP pinout in Figure FEC functionality, which are actually UART 0/1 clear-to-send and request-to-send signals. • Changed maximum core frequency in 166.67MHz. Also, changed symbols in table: f for consistency throughout document and reference manual. • ...

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... Microprocessor Data Sheet, Rev. 3 Figure 9 in Section 4.7, “Pinout—196 from SD_DR_DQS to SD_SDR_DQS. from SD_DQS0 to SD_DQS2 and H3 from Section 5.12.2, “MII Transmit Signal Section 5.12.2, “MII Transmit Section 5, “Electrical Section 5.8, “SDRAM Bus.” Figure 14 and Table 12 and Table 13: Freescale Semiconductor ...

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... MCF5208 ColdFire Freescale Semiconductor ® Microprocessor Data Sheet, Rev. 3 Revision History 45 ...

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