MC908GR32ACFAE Freescale Semiconductor, MC908GR32ACFAE Datasheet - Page 68

• Manufacturer Part Number: MC908GR32ACFAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR32ACFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 1.5KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Analog-to-Digital Converter (ADC)
3.8.2.2 Right Justified Mode
In right justified mode, the ADRH register holds the two MSBs of the
10-bit result. All other bits read as 0. The ADRL register holds the eight LSBs of the 10-bit result. ADRH
and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches
the contents of ADRL until ADRL is read. All subsequent results will be lost until the ADRH and ADRL
reads are completed.
3.8.2.3 Left Justified Signed Data Mode
In left justified signed data mode, the ADRH register holds the eight MSBs of the 10-bit result. The only
difference from left justified mode is that the AD9 is complemented. The ADRL register holds the two
LSBs of the 10-bit result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single
channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. All
subsequent results will be lost until the ADRH and ADRL reads are completed.
68
Address:
Address:
Address:
Address:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Figure 3-6. ADC Data Register High (ADRH) and Low (ADRL)
Figure 3-7. ADC Data Register High (ADRH) and Low (ADRL)
$003D
$003E
$003D
$003E
Bit 7
AD7
Bit 7
AD9
AD1
0
= Unimplemented
= Unimplemented
AD6
AD8
AD0
6
0
6
AD5
AD7
5
0
5
0
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
AD4
AD6
4
0
4
0
AD3
AD5
3
0
3
0
AD4
AD2
2
0
2
0
AD9
AD1
AD3
1
1
0
Freescale Semiconductor
ADRH
ADRL
Bit 0
AD8
AD0
Bit 0
AD2
0