M30262F8GP#U3 Renesas Electronics America, M30262F8GP#U3 Datasheet - Page 152
M30262F8GP#U3
Manufacturer Part Number
M30262F8GP#U3
Description
IC M16C/TINY MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheets
1.M30622SAFPU5.pdf
(308 pages)
2.M30262F4GPU3.pdf
(41 pages)
3.M30262F4GPU3.pdf
(241 pages)
Specifications of M30262F8GP#U3
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30262F8GP#U3M30262F8GP#D3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
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Manufacturer:
Renesas Electronics America
Quantity:
10 000
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UART2 Special Mode Register
144
Figure 1.15.29. Some other functions added
Some other functions added are explained here. Figure 1.15.29 shows their workings.
Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The
bus collision detect interrupt occurs when the R
formity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to “0”.
If this bit is set to “1”, the nonconformity is detected at the timing of the overflow of timer Aj rather than at
the rising edge of the transfer clock.
Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable
bit. Setting this bit to “1” automatically resets the transmit enable bit to “0” when “1” is set in the bus
collision detect interrupt request bit (nonconformity).
Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit
to “1” starts the TxD transmission in synchronization with the falling edge of the RxD terminal.
1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register)
2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register)
3. Transmit start condition select bit (Bit 6 of the UART2 special mode register)
With "1: falling edge of RxD2" selected
0: In normal state
TxD/RxD
CLK
Timer A0
CLK
TxD/RxD
Bus collision
detect interrupt
request bit
Transmit
enable bit
CLK
TxD
RxD
CLK
TxD
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
Enabling transmission
0: Rising edges of the transfer clock
Renesas Technology Corp.
X
D2 level and T
X
D2 level do not match, but the noncon-
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1: Timer A0 overflow
M16C/26 Group
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