MC9S12XEQ384MAL Freescale Semiconductor, MC9S12XEQ384MAL Datasheet - Page 256
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MC9S12XEQ384MAL
Manufacturer Part Number
MC9S12XEQ384MAL
Description
MCU 16BIT 384K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XEP768CAL.pdf
(1328 pages)
Specifications of MC9S12XEQ384MAL
Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
24 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Package
112LQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XEQ384MAL
Manufacturer:
FREESCALE
Quantity:
1 145
Company:
Part Number:
MC9S12XEQ384MAL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 5 External Bus Interface (S12XEBIV4)
5.4.2.4.2
5.4.2.4.3
256
DATA[15:0] (external read)
RW
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (write)
RW
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Bus cycle ->
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (write)
RW
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (write)
RW
Write Access Timing
Read-Write-Read Access Timing
Table 5-18. Interleaved Read-Write-Read Accesses (1 Cycle)
...
...
...
...
...
...
...
...
addr 0
high
...
?
1
?
0
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 5-14. Read Access (n–1 Cycles)
Table 5-17. Write Access (n–1 Cycles)
...
...
...
...
...
...
Table 5-16. Write Access (2 Cycles)
...
...
...
...
...
...
1
Table 5-15. Write Access (1 Cycle)
iqstat-1
acc 0
Access #0
addr 0
addr 0
low
1
?
0
z
high
high
Access #0
?
0
?
0
1
1
1
addr 0
iqstat -1
high
iqstat-1
acc 0
acc 0
z
1
0
low
low
Access #0
Access #0
?
0
?
0
data 0
2
iqstat 0
000
addr 0
low
addr 1
z
1
x
0
high
high
Access #1
Access #1
1
0
data 0
data 0
2
2
2
addr 0
iqstat 0
iqstat 0
high
acc 1
z
1
0
000
low
low
x
1
x
0
data 1
3
0000
000
low
addr 2
addr 1
z
1
x
0
high
high
Access #2
Access #1
1
1
Access #2
...
...
...
...
...
...
...
...
3
3
Freescale Semiconductor
iqstat 1
data 2
acc 2
acc 1
0000
3
low
low
data 0
addr 1
x
1
x
x
1
high
1
Access #1
1
...
...
...
...
...
...
...
...
...
...
...
...
...
...
n
acc 1
0000
low
z
1
x
x
1
...
...
...
...
...
...
...
...
...
...
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