R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 137

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 100 of 802
Table 6.20
X: 0 or 1; —: No change in outcome
Notes:
Port P11_2
SDA
SSO
(RXD2
SCL2
TXD2
SDA2
INT2)
IVREF3
Port P11_3
SCS
(CTS2
RTS2
INT3)
IVCMP3
1. Pulled up by setting the corresponding bit in the P11PUR register to 1.
2. Output drive capacity high by setting the corresponding bit in the P11DRR register to 1.
3. N-channel open-drain output by setting the SOOS bit in the SSMR2 register to 1 (N-channel open-drain output).
4. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1. At this time, set the PD11_2 bit in the PD11
5. N-channel open-drain output by setting the CSOS bit in the SSMR2 register to 1.
6. Synchronous serial communication unit (refer to Table 26.4 Association between Communication Modes and I/O Pins ).
Pin
Pin
register to 0.
Register
Register
i = 2
i = 3
Bit
Bit
Ports P11_2 and P11_3
PD11_i
PD11_i
PD11 INTSR INTEN INTCMP
PD11 INTSR INTEN INTCMP
X
X
X
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
SEL0
SEL0
INTi
INTi
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
INTiEN
INTiEN
Oct 30, 2009
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
INT3
INT3
CP0
CP0
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SSUIICSR ICCR1
IICSEL
—
—
—
—
—
—
—
—
—
—
X
X
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
SSMR2
1
0
0
0
1
0
0
0
0
CSS
ICE
X
X
X
X
X
X
X
X
X
X
0
0
1
0
0
0
0
X
0
0
0
1
0
0
0
0
control
output
CRS
SSU Associated
SSI
X
X
X
X
X
X
X
X
X
X
X
X
X
Register
0
0
0
1
0
0
0
0
0
0
0
1
U2CO
control
CRD
input
SSI
(6)
X
0
X
0
X
1
0
X
0
X
0
X
0
X
0
0
0
X
X
X
X
0
0
X
X
1 0 1 0
X X Other
X X
X X Other
X X
X X
X X
X X
1 0
1 0
X X 0 1
X X 0
X X 0
X X
RXD2
CTSSEL0
SEL
U2SR0
U2SR1
X
X
0
0
1
1
0
0
Other
Other
Other
Other
TXD2
than
than
than
than
than
than
01b
01b
01b
01b
01b
01b
SEL
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Other than
X
X
2
0
0
1
1
0
2
U2MR
U2MR
SMD
SMD
000b
1
X
X
X
X
X
X
X
X
1
0
0
1
1
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
0
0
0
U2SMR
IICM
—
X
X
0
0
0
0
0
0
0
0
1
0
1
Input port
Output port
SDA input/output
SSO input
SSO output
RXD2 input
SCL2
input/output
TXD2 output
SDA2
input/outpu
INT2 input
Comparator B3
reference voltage
input (IVREF3)
Input port
Output port
SCS input
SCS output
CTS2 input
RTS2 output
INT3 input
Comparator B3
input (IVCMP3)
Function
Function
6. I/O Ports
(1)
(1)
(1)
(1)
(1)
(1)
(2, 4)
(2)
(2)
(1)
(2, 3)
(1)
(2, 5)
(2, 4)
(2, 4)
(2)
(2)