HD64F3687FP Renesas Electronics America, HD64F3687FP Datasheet - Page 209

• Manufacturer Part Number: HD64F3687FP
• Description: IC H8 MCU FLASH 56K 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3687FP

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

The timer Z has a 16-bit timer with two channels. Figures 13.1, 13.2, and 13.3 show the block
diagrams of entire timer Z, its channel 0, and its channel 1, respectively. For details on the timer Z
functions, refer to table 13.1.
13.1
TIM08Z0A_000120030300
Capability to process up to eight inputs/outputs
Eight general registers (GR): four registers for each channel
Selection of five counter clock sources: four internal clocks ( , /2, /4, and /8) and an
external clock
Seven selectable operating modes
High-speed access by the internal 16-bit bus
Any initial timer output value can be set
Output of the timer is disabled by external trigger
Independently assignable output compare or input capture functions
Output compare function
Selection of 0 output, 1 output, or toggle output
Input capture function
Rising edge, falling edge, or both edges
Synchronous operation
Timer counters_0 and _1 (TCNT_0 and TCNT_1) can be written simultaneously.
Simultaneous clearing by compare match or input capture is possible.
PWM mode
Up to six-phase PWM output can be provided with desired duty ratio.
Reset synchronous PWM mode
Three-phase PWM output for normal and counter phases
Complementary PWM mode
Three-phase PWM output for non-overlapped normal and counter phases
The A/D conversion start trigger can be set for PWM cycles.
Buffer operation
The input capture register can be consisted of double buffers.
The output compare register can automatically be modified.
16-bit TCNT and GR registers can be accessed in high speed by a 16-bit bus interface
Features
Section 13 Timer Z
Rev.5.00 Nov. 02, 2005 Page 175 of 500
Section 13 Timer Z
REJ09B0027-0500