C8051F012-GQ Silicon Laboratories Inc, C8051F012-GQ Datasheet - Page 29
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C8051F012-GQ
Manufacturer Part Number
C8051F012-GQ
Description
IC 8051 MCU 32K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F01xr
Specifications of C8051F012-GQ
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 4x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
8
Number Of Timers
4 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F005DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
On-chip Dac
12 bit, 2 Channel
Data Rom Size
32 KB
A/d Bit Size
10 bit
A/d Channels Available
4
Height
1.4 mm
Length
7 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
7 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1193
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F012-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F012-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
5. ADC (12-Bit, C8051F000/1/2/5/6/7 Only)
The ADC subsystem for the C8051F000/1/2/5/6/7 consists of a 9-channel, configurable analog multiplexer
(AMUX), a programmable gain amplifier (PGA), and a 100ksps, 12-bit successive-approximation-register ADC
with integrated track-and-hold and programmable window detector (see block diagram in Figure 5.1). The AMUX,
PGA, Data Conversion Modes, and Window Detector are all configurable under software control via the Special
Function Register’s shown in Figure 5.1. The ADC subsystem (ADC, track-and-hold and PGA) is enabled only
when the ADCEN bit in the ADC Control register (ADC0CN, Figure 5.7) is set to 1. The ADC subsystem is in low
power shutdown when this bit is 0. The Bias Enable bit (BIASE) in the REF0CN register (see Figure 9.2) must be
set to 1 in order to supply bias to the ADC.
5.1.
Eight of the AMUX channels are available for external measurements while the ninth channel is internally
connected to an on-board temperature sensor (temperature transfer function is shown in Figure 5.3). Note that the
PGA gain is applied to the temperature sensor reading. AMUX input pairs can be programmed to operate in either
the differential or single-ended mode. This allows the user to select the best measurement technique for each input
channel, and even accommodates mode changes “on-the-fly”. The AMUX defaults to all single-ended inputs upon
reset. There are two registers associated with the AMUX: the Channel Selection register AMX0SL (Figure 5.5),
and the Configuration register AMX0CF (Figure 5.4). The table in Figure 5.5 shows AMUX functionality by
channel for each possible configuration. The PGA amplifies the AMUX output signal by an amount determined by
the AMPGN2-0 bits in the ADC Configuration register, ADC0CF (Figure 5.6). The PGA can be software-
programmed for gains of 0.5, 1, 2, 4, 8 or 16. It defaults to unity gain on reset.
29
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
Analog Multiplexer and PGA
SENSOR
AGND
TEMP
AMX0CF
ADC0GTH
Figure 5.1. 12-Bit ADC Functional Block Diagram
+
+
+
+
-
-
-
-
AMUX
(SE or
9-to-1
DIFF)
AMX0SL
ADC0GTL
X
+
-
AV+
ADCEN
Rev. 1.7
AGND
ADC0CF
ADC0LTH
ADC
12-Bit
AV+
SAR
ADC0CN
ADC0LTL
12
24
12
COMB
LOGIC
ADWINT