MC68HC705C9ACFBE Freescale Semiconductor, MC68HC705C9ACFBE Datasheet - Page 77

• Manufacturer Part Number: MC68HC705C9ACFBE
• Description: IC MCU 8BIT 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C9ACFBE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 352 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Processor Series: HC705C
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 352 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 31
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Package: 44PQFP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Bits 5 and 3–0 — Not Implemented
10.5.3 Serial Peripheral Data I/O Register
The serial peripheral data I/O register (SPDR), shown in
on the serial bus. Only a write to this register will initiate transmission/reception of another byte and this
will only occur in the master device. At the completion of transmitting a byte of data, the SPIF status bit is
set in both the master and slave devices.
When the user reads the serial peripheral data I/O register, a buffer is actually being read. The first SPIF
must be cleared by the time a second transfer of the data from the shift register to the read buffer is
initiated or an overrun condition will exist. In cases of overrun, the byte which causes the overrun is lost.
A write to the serial peripheral data I/O register is not buffered and places data directly into the shift
register for transmission.
Freescale Semiconductor
Clearing the MODF bit is accomplished by reading the SPSR (with MODF set), followed by a write to
the SPCR. Control bits SPE and MSTR may be restored by user software to their original state during
this clearing sequence or after the MODF bit has been cleared. When configured as an
MC68HC05C9A, it is also necessary to restore DDRD after a mode fault.
These bits always read 0.
$000C
Reset:
Read:
Write:
SPD7
Bit 7
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
SPD6
Figure 10-6. PI Data Register (SPDR)
6
SPD5
5
Unaffected by reset
SPD4
4
Figure
SPD3
3
10-6, is used to transmit and receive data
SPD2
2
SPD1
1
SPD0
Bit 0
SPI Registers
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