MCF5271CVM100J Freescale Semiconductor, MCF5271CVM100J Datasheet - Page 8
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MCF5271CVM100J
Manufacturer Part Number
MCF5271CVM100J
Description
IC MCU 166MHZ 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5271CVM100J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
61
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
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5.1
5.1.1
5.1.2
5.1.3
5.1.3.1
5.1.3.2
5.1.3.3
5.1.3.4
5.1.3.5
5.2
5.2.1
5.2.1.1
5.2.1.2
6.1
6.1.1
6.1.2
6.2
6.2.1
6.2.2
6.2.3
6.2.4
7.1
7.1.1
7.1.2
7.1.3
7.1.3.1
7.1.3.2
7.1.3.3
7.1.3.4
viii
Paragraph
Number
Introduction..................................................................................................................... 5-1
Memory Map/Register Definition .................................................................................. 5-6
Introduction..................................................................................................................... 6-1
Register Description ....................................................................................................... 6-1
Introduction..................................................................................................................... 7-1
Features....................................................................................................................... 5-1
Physical Organization ................................................................................................. 5-1
Operation .................................................................................................................... 5-3
Registers Description.................................................................................................. 5-7
Features....................................................................................................................... 6-1
Operation .................................................................................................................... 6-1
SRAM Base Address Register (RAMBAR)............................................................... 6-2
SRAM Initialization.................................................................................................... 6-4
SRAM Initialization Code .......................................................................................... 6-4
Power Management .................................................................................................... 6-5
Block Diagram............................................................................................................ 7-2
Features....................................................................................................................... 7-4
Modes of Operation .................................................................................................... 7-4
Interaction with Other Modules.............................................................................. 5-3
Memory Reference Attributes ................................................................................ 5-4
Cache Coherency and Invalidation......................................................................... 5-4
Reset ....................................................................................................................... 5-5
Cache Miss Fetch Algorithm/Line Fills ................................................................. 5-5
Cache Control Register (CACR) ............................................................................ 5-7
Access Control Registers (ACR0, ACR1)............................................................ 5-10
Normal PLL Mode with Crystal Reference............................................................ 7-5
Normal PLL Mode with External Reference.......................................................... 7-5
1:1 PLL Mode......................................................................................................... 7-5
External Clock Mode (Bypass Mode) .................................................................... 7-5
MCF5271 Reference Manual, Rev. 2
Static RAM (SRAM)
Clock Module
Contents
Chapter 5
Chapter 6
Chapter 7
Cache
Title
Freescale Semiconductor
Number
Page
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